• Proceedings of the Korean Society of Computer Information Conference
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• 2017.07a
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• pp.3-4
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• 2017

DRAM, HDD의 성장세가 둔화되면서 NVM이 그 대안으로 떠오르고 있다. Xpoint, Z-SSD등 여러 고성능 NVM이 발표되고 있으며 DRAM의 성능을 목표로 하고 있다. 본 논문에서는 DRAM 수준의 고성능 NVM이 상용화 될 때 어느 정도의 성능과 가격지표를 보일 것이며 이에 대한 가격과 저장공간의 트레이드오프는 어느 정도일지 알아보기 위해 실험을 진행하였다. RAM disk로 NVM환경을 시뮬레이션 하였고 SSD, HDD 간 I/O 성능을 측정하였다. NVM과 SSD는 70배에서 200배, NVM과 디스크는 98배에서 3000배 이상 차이가 있음을 확인했다. 이 결과를 바탕으로 RAM disk와 SSD 가격지표를 조사하여 IOPS/$를 도출해 보았고 NVM이 7배의 IOPS/$를 가지지만 SSD가 18배의 GB/$를 가지는 것을 확인할 수 있었다.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.87-95
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• 2016

Nonvolatile memory (NVM) is being considered as an alternative of traditional memory devices such as SRAM and DRAM, which suffer from various limitations due to the technology scaling of modern integrated circuits. Although NVMs have advantages including nonvolatility, low leakage current, and high density, their inferior write performance in terms of energy and endurance becomes a major challenge to the successful design of NVM-based memory systems. In order to overcome the aforementioned drawback of the NVM, extensive research is required to develop energy- and endurance-aware optimization techniques for NVM-based memory systems. However, researchers have experienced difficulty in finding a suitable simulation tool to prototype and evaluate new NVM optimization schemes because existing simulation tools do not consider the feature of NVM devices. In this article, we introduce a NVM-based cache simulator to support rapid prototyping and evaluation of NVM-based caches, as well as energy- and endurance-aware NVM cache optimization schemes. We demonstrate that the proposed NVM cache simulator can easily prototype PRAM cache and PRAM+STT-RAM hybrid cache as well as evaluate various write traffic reduction schemes and wear leveling schemes.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.4
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• pp.65-69
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• 2019

This paper presents an optimized adoption of NVM for the storage system considering application characteristics. To do so, we first characterize the storage access patterns for different application types, and make two prominent observations that can be exploited in allocating NVM storage efficiently. The first observation is that a bulk of I/O does not happen on a single storage partition, but it is varied significantly for different application categories. Our second observation is that there exists a large proportion of single accessing in storage data. Based on these observations, we show that maximizing the storage performance with NVM is not obtained by fixing it as a specific storage partition but by allocating it adaptively for different applications. Specifically, for graph, database, and web applications, using NVM as a swap, a journal, and a file system partitions, respectively, performs well.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.1-6
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• 2017

This paper presents an optimized adoption of NVM for the storage system of heterogeneous applications. Our analysis shows that a bulk of I/O does not happen on a single storage partition, but it is varied significantly for different application categories. In particular, journaling I/O accounts for a dominant portion of total I/O in DB applications like OLTP, whereas swap I/O accounts for a large portion of I/O in graph visualization applications, and file I/O accounts for a large portion in web browsers and multimedia players. Based on these observations, we argue that maximizing the performance gain with NVM is not obtained by fixing it as a specific storage partition but varied widely for different applications. Specifically, for graph visualization, DB, and multimedia player applications, using NVM as a swap, a journal, and a file system partitions, respectively, performs well. Our optimized adoption of NVM improves the storage performance by 10-61%.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.136-136
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• 2011

반도체 및 전자기기 산업에 있어서 NVM은 아주 중요한 부분을 차지하고 있다. NVM은 디스플레이 분야에 많은 기여를 하고 있는데, 측히 AMOLED에 적용이 가능하여 온도에 따라 변하는 구동 전류, 휘도, color balance에 따른 문제를 해결하는데 큰 역할을 한다. 본 연구에서는 bottom gate 구조의 nc-Si NVM 실험을 진행하였다. P-type silicon substrate (0.01~0.02 ${\Omega}-cm$) 위에 Blocking layer 층인 SiO2 (SiH4:N2O=6:30)를 12.5nm증착하였고, Charge trap layer 층인 SiNx (SiH4:NH3=6:4)를 20 nm 증착하였다. 마지막으로 Tunneling layer 층인 SiOxNy은 N2O (2.5 sccm) 플라즈마 처리를 통해 2.5 nm 증착하였다. 이러한 ONO 구조층 위에 nc-Si을 50 nm 증착후에 Source와 Drain 층을 Al 120 nm로 evaporator 이용하여 증착하였다. 제작한 샘플을 전기적 특성인 Threshold voltage, Subthreshold swing, Field effect mobility, ON/OFF current ratio, Programming & Erasing 특성, Charge retention 특성 등을 알아보았다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.741-749
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• 2014

Low power double data rate 2 non-volatile memory (LPDDR2-NVM) has been deemed the standard interface to connect non-volatile memory devices such as phase-change memory (PCM) directly to the main memory bus. However, most of the previous literature does not consider or overlook this standard interface. In this paper, we propose address phase skipping by reforming the way of interfacing with LPDDR2-NVM. To verify effectiveness and functionality, we also develop a system-level prototype that includes our customized LPDDR2-NVM controller and commercial PCM devices. Extensive simulations and measurements demonstrate up to a 3.6% memory access time reduction for commercial PCM devices and a 31.7% reduction with optimistic parameters of the PCM research prototypes in industries.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.60-61
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• 2007

In this paper, the p-channel poly Si thin-film transistors (Poly-Si TFT's) using formed by solid phase crystallization (SPC) on glass substrate were fabricated. And we propose an ONO(Oxide-Nitride-Oxide) multilayer as the gate insulator for poly-Si TFT's to indicate non-volatile memory (NVM) effect. Poly-Si TFT is investigated by measuring the electrical properties of poly-Si films, such as I-V characteristics, on/off current ratio. NVM characteristics is showed by measuring the threshold voltage change of TFT through I-V characteristics.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.79-86
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• 2019

For decades, in-memory data structures have been designed for DRAM-based main memory that provides symmetric read/write performances and has no limited write endurance. However, such data structures provide sub-optimal performance for NVM as it has different characteristics to DRAM. With this motivation, we rethink a conventional red-black tree in terms of its efficacy under NVM settings. The original red-black tree constantly rebalances sub-trees so as to export fast access time over dataset, but it inevitably increases the write traffic, adversely affecting the performance for NVM with a long write latency and limited endurance. To resolve this problem, we present a variant of the red-black tree called a hierarchical balanced binary search tree. The proposed structure maintains multiple keys in a single node so as to amortize the rebalancing cost. The performance study reveals that the proposed hierarchical binary search tree effectively reduces the write traffic by effectively reaping the high capacity of NVM.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.317-317
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• 2016

이 연구에서는 산화막/산화막/산화막 적층구조의 블로킹산화막/전하저장층/터널링산화막과 InSnZnO를 채널층으로 이용한 비휘발성 메모리 (NVM) 소자의 메모리 특성을 확인하였다. NVM 소자의 기본 전기적 특성의 경우 $19.8cm2/V{\cdot}s$의 높은 전계효과 이동도, 0.09V의 낮은 문턱전압, 0.127 V/dec의 낮은 기울기 및 $1.47{\times}107$의 높은 전류점멸비를 나타내었다. 또한, InSnZnO의 경우 가시광영역에서 85% 이상의 투과도를 가짐을 확인하였다. NVM소자의 경우, +12V의 Programming과 1ms의 Programming duration time에서 104s 이후 86%이상의, 그리고 10년 후 67% 이상의 우수한 전하보유시간 특성을 나타내었다. 이를 통해 투명플렉서블 메모리 시스템에 산화막/산화막/산화막 적층구조의 InSnZnO NVM소자의 응용 가능성이 높다고 판단한다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.2
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• pp.76-80
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• 2014

Dual-gate PCRAM which unify capacitor-less DRAM and NVM using a PCM instead of a typical SONOS flash memory is proposed as 1 transistor. $VO_2$ changes its phase between insulator and metal states by temperature and field. The front-gate and back-gate control NVM and DRAM, respectively. The feasibility of URAM is investigated through simulation using c-interpreter and finite element analysis. Threshold voltage of NVM is 0.5 V that is based on measured results from previous fabricated 1TPCM with $VO_2$. Current sensing margin of DRAM is 3 ${\mu}A$. PCM does not interfere with DRAM in the memory characteristics unlike SONOS NVM. This novel unified dual-gate PCRAM reported in this work has 1 transistor, a low RESET/SET voltage, a fast write/erase time and a small cell so that it could be suitable for future production of URAM.