• Journal of Power Electronics
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• v.5 no.3
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• pp.224-232
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• 2005

A new three phase three-level Pulse Width Modulation (PWM) Switched Voltage Source (SVS) inverter with zero neutral point potential is proposed. It consists of three single-phase inverter modules. Each module is composed of a switched voltage source and inverter switches. The major advantage is that the peak value of the phase output voltage is twice as high as that of a conventional neutral-point-clamped (NPC) PWM inverter. Thus, the proposed inverter is suitable for applications with low voltage sources such as batteries, fuel cells, or solar cells. Furthermore, three-level waveforms of the proposed inverter can be achieved without the switch voltage imbalance problem. Since the average neutral point potential of the proposed inverter is zero, a common ground between the input stage and the output stage is possible. Therefore, it can be applied to a transformer-less Power Conditioning System (PCS). The proposed inverter is verified by a PSpice simulation and experimental results based on a laboratory prototype.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.101-103
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• 2007

Since they use the low switching frequency in multilevel inverter systems, they generate the high low frequency harmonic components. Generally, LC filter is used at the output terminal of inverter systems to solve this problem. But it causes a voltage drop at the output terminal by use of damping resistors, and causes the problem in which system efficiency decreases due to power loss of the damping resistor. In this paper, we proposed an output filter design method for NPC three-level inverter systems with low switching frequency. And we analyzed the efficiency of the proposed filter system, and the effectiveness of the proposed system is verified by simulation and experimental results.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1207-1216
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• 2015

In order to suppress the low frequency oscillation of the neutral-point voltage for three-level inverters, this paper proposes a new discontinuous pulse width modulation (DPWM) control method. The conventional sinusoidal pulse width modulation (SPWM) control has no effect on balancing the neutral-point voltage. Based on the basic control principle of DPWM, the relationship between the reference space voltage vector and the neutral-point current is analyzed. The proposed method suppresses the low frequency oscillation of the neutral-point voltage by keeping the switches of a certain phase no switching in one carrier cycle. So the operating time of the positive and negative small vectors is equal. Comparing with the conventional SPWM control method, the proposed DPWM control method suppresses the low frequency oscillation of the neutral-point voltage, decreases the output waveform harmonics, and increases both the output waveform quality and the system efficiency. An experiment has been realized by a neutral-point clamped (NPC) three-level inverter prototype based on STM32F407-CPLD. The experimental results verify the correctness of the theoretical analysis and the effectiveness of the proposed DPWM method.

• Journal of Power Electronics
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• v.12 no.2
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• pp.344-356
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• 2012

In recent years, multilevel technology has become an effective and practical solution in the field of moderate and high voltage applications. This paper discusses an APF with a three-level NPC inverter. Obviously, the application of such converter to APFs is hindered by the problem of the voltage unbalance of DC capacitors, which leads to system instability. This paper comprehensively analyzes the theoretical limitations of the neutral-point voltage balancing problem for tracking different harmonic currents utilizing current switching functions from the space vector PWM (SVPWM) point of view. The fluctuation of the neutral point caused by the load currents of certain order harmonic frequency is reported and quantified. Furthermore, this paper presents a close-loop digital control algorithm of the DC voltage for this APF. A PI controller regulates the DC voltage in the outer-loop controller. In the current-loop controller, this paper proposes a simple neutral-point voltage control method. The neutral-point voltage imbalance is restrained by selecting small vectors that will move the neutral-point voltage in the direction opposite the direction of the unbalance. The experiment results illustrate that the performance of the proposed approach is satisfactory.

• Journal of Power Electronics
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• v.19 no.1
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• pp.146-157
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• 2019

The inverter is an essential part of permanent magnet synchronous motor (PMSM) drive systems. The performance of an inverter is greatly influenced by its modulation strategy. Using a proper management of modulation strategies can guarantee high performance from a PMSM under various speed conditions. Switching between modulations is a pivotal technique that determines the performance of a PMSM. Most works on hybrid methods focus on two-level induction motors drive systems. In this paper, in order to improve the performance of PMSMs under various speed conditions, a hybrid method of a pulse width modulation (PWM) control scheme based on a neutral-point-clamped (NPC) three level topology was proposed. This hybrid PWM modulation comprised space vector PWM (SVPWM) and selective harmonic elimination PWM (SHEPWM). Under low speed conditions, the SVPWM is employed to cause the PMSM to start smoothly, and to obtain a rapid response from the control system. Under high speed conditions, the SHEPWM is employed to reduce the switching frequency and to eliminate particular current harmonics. Moreover, the harmonic characteristics of different modulations are analyzed to obtain a smooth transition between the SHEPWM and the SVPWM. Experimental and simulation results indicated the effectiveness of the proposed control method.

• Journal of Power Electronics
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• v.19 no.3
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• pp.727-743
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• 2019

This paper presents a pulse-width modulation strategy to eliminate the common mode voltage (CMV) with reduced CMV spikes in multilevel inverters since a high CMV magnitude and its fast variations dv/dt result in bearing failure of motors, overvoltage at motor terminals, and electromagnetic interference (EMI). The proposed method only utilizes the zero CMV states in a space vector diagram and it is implemented by a carrier-based pulse-width modulation (CBPWM) method. This method is generalized for odd number levels of inverters including neutral-point-clamped (NPC) and cascaded H-bridge inverters. Then it is extended to the over-modulation mode. The over-modulation mode is implemented by using the two-limit trajectory principle to maintain linear control and to avoid look-up tables. Even though the CMV is eliminated, CMV spikes that can cause EMI and bearing current problems still exist due to the deadtime effect. As a result, the deadtime effect is analyzed. By taking the deadtime effect into consideration, the proposed method is capable of reducing CMV spikes. Simulation and experimental results verify the effectiveness of the proposed strategy.

• Journal of Power Electronics
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• v.18 no.1
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• pp.70-80
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• 2018

A novel strategy based on a zero common mode voltage pulse-width modulation (ZCMV-PWM) technique and zero-sequence circulating current (ZSCC) feedback control is proposed in this study to eliminate ZSCCs between three-level neutral point clamped (NPC) voltage source inverters, with common AC and DC buses, that are operating in parallel. First, an equivalent model of ZSCC in a three-phase three-level NPC inverter paralleled system is developed. Second, on the basis of the analysis of the excitation source of ZSCCs, i.e., the difference in common mode voltages (CMVs) between paralleled inverters, the ZCMV-PWM method is presented to reduce CMVs, and a simple electric circuit is adopted to control ZSCCs and neutral point potential. Finally, simulation and experiment are conducted to illustrate effectiveness of the proposed strategy. Results show that ZSCCs between paralleled inverters can be eliminated effectively under steady and dynamic states. Moreover, the proposed strategy exhibits the advantage of not requiring carrier synchronization. It can be utilized in inverters with different types of filter.

• Journal of Power Electronics
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• v.13 no.2
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• pp.243-249
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• 2013

This paper presents a neutral-point voltage balancing method for three-level inverter systems using a time-offset estimation scheme. The neutral-point voltage is balanced by adding a time-offset to the turn-on time of the switches. If an inaccurate time-offset is added, the neutral-point deviation still remains. An accurate time-offset is obtained through the proposed time-offset estimation scheme. This method is implemented without additional hardware, complex calculations, or analysis. The effectiveness of the proposed method is verified by experiments.

• Journal of Electrical Engineering and Technology
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• v.2 no.4
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• pp.505-512
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• 2007

The object of this paper is to study a new control structure for sensorless induction machines dedicated to electrical drives using a three-level voltage source inverter VSI-NPC. The amplitude and the rotating speed of the flux vector can be controlled freely. The scheme investigated is an Enhanced direct torque control "EDTC" for electric vehicle propulsion. The considered application imposes some constraints which are achieved in EDTC control (fast torque response, optimal switching logic, torque control at zero speed, and large speed control. The results obtained for an induction motor indicate superior performance over the FOC type without need for any mechanical sensor.

• Proceedings of the KIPE Conference
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• 2003.11a
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• pp.11-16
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• 2003

The 3-level converter/inverter system is very efficient in the ac motor drives of high voltage and high power application. This paper proposed a simple method to diagnose faults using change of current vector pattern in space vector diagram when the faults occurrence in the 3-level inverter and a control method that can protect system from unbalance of the neutral point voltage according to faults. The validity of the proposed method is demonstrated by the simulation results.