• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.11a
• /
• pp.35-38
• /
• 2002

In this paper, the characteristics of channel hot electron (CHE) injection for the write operation in a NOR-type SONOS flash memory with common source line were investigated. The thicknesses of he tunnel oxide, the memory nitride， and the blocking oxide layers for the gate insulator of the fabricated SONOS devices were $34{\AA}$, $73{\AA}$, and $34{\AA}$, respectively. The SONOS devices compared to floating gate devices have many advantages, which are a simpler cell structure, compatibility with conventional logic CMOS process and a superior scalability. For these reasons, the introduction of SONOS device has stimulated. In the conventional SONOS devices, Modified Folwer-Nordheim (MFN) tunneling and CHE injection for writing require high voltages, which are typically in the range of 9 V to 15 V. However CHE injection in our devices was achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The memory window of about 3.2 V and the write speed of $100{\mu}s$ were obtained. Also, the disturbance and drain turn-on leakage during CHE injection were not affected in the SONOS array. These results show that CHE injection can be achieved with a low voltage and single power supply, and applied for the high speed program of the SONOS memory devices.

• Journal of the Korea Computer Industry Society
• /
• v.2 no.2
• /
• pp.219-228
• /
• 2001

This paper presents the implementation of comparator which are Fail-Safe with respect to faults caused by any single physical defect likely to occur in NMOS and CMOS integrated circuit. The goal is to use it at the Fail-Safe system. First, a new fault model for PLA(Programmable Logic Array) is presented. This model reflects several physical defects in VLSI circuits. It focuses on designs based on PLA because VLSI chips are far too complex to allow detailed analysis of all the possible physical defects that can occur and of the effects on the operation of the circuit. Second, this paper show that these design, which was implemented with 2 level AND_ORor NOR-NOR circuit, are optimal in term of size. And it also present a formal proof that a comparator implemented as NOR-NOR PLA, based on these design, is self-testing with respect to most single faults in the presented fault model. Finally, it discuss the application of the self-testing comparator as a building block for implementing Fail-Safe Adder.

• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 1984.10a
• /
• pp.25-27
• /
• 1984

Using LED sources, the system that performs optical logic function of the input data arrays will be presented. Sixteen possible functions of two binary data arrays, such as AND, OR, NOR and XOR are simply obtained in parallel by controlling LED switching mode. Experimental result and some examples of application will be given.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.11a
• /
• pp.117-120
• /
• 2005

The SONOS devices have been fabricated by the conventional $0.35{\mu}m$ complementary metal-oxide-semiconductor (CMOS) process with NOR array. Two-bit operation using conventional process achieve the high density memory compare with other two-bit memory. Lateral diffusion phenomenon in the two-bit operation cause soft error in the memory. In this study, the programming conditions arc investigated in order to reduce lateral diffusion for two-bit operation of CSL-NOR type SONOS flash cell.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.28B no.11
• /
• pp.859-865
• /
• 1991

The paper proposes a design of high-speed dynamic CMOS PLA (Programmable Logic Array) which performs stable circuit operation. The race problem which nay occur in a NOR-NOR implementation of PLA is free in the proposed dynamic CMOS PLA by delaying time between the clocks to the AND- and to the OR-planes. The delay element has the same structure as the product line of the longest delay in the AND p`ane. Therefore it is unnecessary to design the delay element or to calculate correct delay time. The correct delay generated by the delay element makes the dynamic CMOS PLA to perform correct and stable circuit operation. Theproposed dynamic CMOS PLA has few variation of switching delay with the increasing number of inputs or outputs in PLA. It is verified by SPICE circuit simulation that the proposed dynamic CMOS PLA has the better performance over existing dynamic CMOS PLA's.

• Communications for Statistical Applications and Methods
• /
• v.6 no.2
• /
• pp.585-594
• /
• 1999

Let {$X_{nj}$, 1$\leq$j$\leq$n,j$\geq$1} be a triangular array of random variables which are neither independent nor identically distributed. The almost sure convergences of randomly weighted partial sums of the form $$\sum_n^{j=1}$$ $W_{nj}$$X_{nj} are studied where {Wnj 1$\leq$j$\leq$n, j$\geq$1} is a triangular array of random weights. Application regarding the Efron bootstrap is also introduced.

• 제어로봇시스템학회:학술대회논문집
• /
• 1996.10a
• /
• pp.409-412
• /
• 1996

Ultrasonic sensors are widely used in various applications due to advantages of low cost, simplicity in construction, mechanical robustness, and little environmental restriction in usage. But the main purposes of the noncontact sensing are rather narrowly confined within object detection and distance measurement. For the application of object recognition, ultrasonic sensors exhibit several shortcomings of poor directionality which results in low spatial resolution of objects, and specularity which gives frequent erroneous range readings. To resolve these problems in object recognition, an array of the sensor has been used. To improve the spatial resolution, more number of sensors are used in essence throughout the various devices of the sensor arrays. Under the disguise of a fixed number of the sensors, the array can be shifted mechanically in several steps. In this paper we propose a practical sensor resolution enhancement method using an electronic circuit accompanying the sensor array. The circuit changes the transmitter output voltage in several steps. Using the known sensor characteristics, a set of different return echo signals provide enhanced spatial resolution. The improvement is obtained with neither the cost of the increased number of the sensors nor extra mechanical devices.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.389-392
• /
• 2005

In the maskless photolithography based on the Digital Micromirror Device (DMD) by Texas Instruments Inc. (TI), the micromirror array works as a virtual photomask to write patterns directly onto Flat Panel Display (FPD) at high speed with low cost. However, it is neither simple to generate region-based patterns for the micromirror array nor easy to deliver sequences of patterns for the micromirror controller. Moreover, the quality of lithography yields the precise synchronization between generating sequence of patterns and irradiation rate off micromirrors. In this study, the region-based pattern generating system for maskless photolithography is devised. To verify salient features of devised functionalities, the prototype system is implemented and the system is evaluated with actual DMD based photolithography. The results show that proposed pattern generating method is proper and reliable. Moreover, the devised region-based pattern generating system is robust and precise enough to handle any possible user specified mandate and to achieve the quality of photolithography required by FPD manufacturer.

• Journal of Sensor Science and Technology
• /
• v.6 no.4
• /
• pp.298-306
• /
• 1997

Ultrasonic sensors are widely used in various applications due to advantages of low cost, simplicity in construction, mechanical robustness, and little environmental restriction in usage. But the main purposes of the noncontact sensors are rather narrowly confined within object detection and distance measurement. For the application of object recognition, ultrasonic sensors exhibit several shortcomings of poor directionality which results in low spatial resolution of an object, and specularity which gives frequent erroneous range readings. To resolve these problems in object recognition, an array of the sensors has been used. To improve the spatial resolution, more number of sensors are used in essence throughout the various devices of the sensor arrays. Under the disguise of a fixed number of the sensors, the array can be shifted mechanically in several steps. In this paper we propose a practical sensor resolution enhancement method using an electronic circuit accompanying the sensor array. The circuit changes the transmitter output voltage in several steps. Using the known sensor characteristics, a set of different return echo signals provide enhanced spatial resolution. The improvement is obtained without the cost of the increased number of the sensors nor extra mechanical devices.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.4
• /
• pp.26-33
• /
• 2012

As the flash memory has increased the market share of data storage in imbedded system and occupied the most of area in a system, It has a profound impact on system reliability. Flash memory is divided NOR/NAND-type according to the cell array structure, and is classified as SLC(Single Level Cell)/MLC(Multi Level Cell) according to reference voltage. Although NAND-type flash memory is slower than NOR-type, but it has large capacity and low cost. Also, By the effect of demanding mobile market, MLC NAND-type is widely adopted for the purpose of the multimedia data storage. Accordingly, Importance of fault detection algorithm is increasing to ensure MLC NAND-type flash memory reliability. There are many researches about the testing algorithm used from traditional RAM to SLC flash memory and it detected a lot of errors. But the case of MLC flash memory, testing for fault detection, there was not much attempt. So, In this paper, Extend SLC NAND-type flash memory fault detection algorithm for testing MLC NAND-type flash memory and try to reduce these differences.