• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.144-151
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• 2022

In this paper, a 1.5V 256kb eFlash memory IP with low area DC-DC converter is designed for battery application. Therefore, in this paper, 5V NMOS precharging transistor is used instead of cross-coupled 5V NMOS transistor, which is a circuit that precharges the voltage of the pumping node to VIN voltage in the unit charge pump circuit for the design of a low-area DC-DC converter. A 5V cross-coupled PMOS transistor is used as a transistor that transfers the boosted voltage to the VOUT node. In addition, the gate node of the 5V NMOS precharging transistor is made to swing between VIN voltage and VIN+VDD voltage using a boost-clock generator. Furthermore, to swing the clock signal, which is one node of the pumping capacitor, to full VDD during a small ring oscillation period in the multi-stage charge pump circuit, a local inverter is added to each unit charge pump circuit. And when exiting from erase mode and program mode and staying at stand-by state, HV NMOS transistor is used to precharge to VDD voltage instead of using a circuit that precharges the boosted voltage to VDD voltage. Since the proposed circuit is applied to the DC-DC converter circuit, the layout area of the 256kb eFLASH memory IP is reduced by about 6.5% compared to the case of using the conventional DC-DC converter circuit.

• ETRI Journal
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• v.37 no.1
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• pp.97-106
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• 2015

In this paper, MOS-triggered silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR-based ESD protection circuits with floating N+/P+ diffusion regions for inverter and light-emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded-gate NMOS (ggNMOS) in the MOS-triggered SCR-based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P-well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the N+/P+ floating diffusion region. The trigger voltage was improved by the partial insertion of a P-body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low- and high-voltage applications were designed using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology, with $100{\mu}m$ width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS-6008).

• Journal of Electrical Engineering and Technology
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• v.8 no.5
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• pp.1182-1187
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• 2013

Transient radiation is emitted during a nuclear explosion and causes fatal errors as upset and latch-up in CMOS circuits. This paper proposes the transient radiation SPICE models of NMOS, PMOS, and INVERTER based on the transient radiation analysis using TCAD (Technology Computer Aided Design). To make the SPICE model of a CMOS circuit, the photocurrent in the PN junction of NMOS and PMOS was replaced as current source, and a latch-up phenomenon in the inverter was applied using a parasitic thyristor. As an example, the proposed transient radiation SPICE model was applied to a CMOS NAND circuit. The CMOS NAND circuit was simulated by SPICE and TCAD using the 0.18um CMOS process model parameter. The simulated results show that the SPICE results were similar to the TCAD simulation and the test results of commercial CMOS NAND IC. The simulation time was reduced by 120 times compared to the TCAD simulation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.6
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• pp.428-435
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• 1998

SOI-like-bulk CMOS device is proposed, which having the advantages of SOI(Silicon On Insulator) and protects short channel effects efficiently with adding partial epitaxial process at standard CMOS process. SOI-like-bulk NMOS and PMOS with 0.25${\mu}{\textrm}{m}$ gate length have designed and optimized through analyzing the characteristics of these devices and applying again to the design of processes. The threshold voltages of the designed NMOS and PMOS are 0.3[V], -0.35[V] respectively and those have shown the stable characteristics under 1.5[V] gate and drain voltages. The leakage current of typical bulk-CMOS increase with shortening the channel length, but the proposed structures on this a study reduce the leakage current and improve the subthreshold characteristics at the same time. In addition, subthreshold swing value, S is 70.91[mV/decade] in SOI-like-bulk NMOS and 63.37[mV/ decade] SOI-like-bulk PMOS. And the characteristics of SOI-like-bulk CMOS are better than those of standard bulk CMOS. To validate the circuit application, CMOS inverter circuit has designed and transient & DC transfer characteristics are analyzed with mixed mode simulation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.7
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• pp.437-440
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• 2017

We report on amorphous thin-film transistors (TFTs) with indium zinc oxide (IZO) channel layers that were fabricated via a solution process. We prepared the IZO semiconductor solution with 0.1 M indium nitrate hydrate and 0.1 M zinc acetate dehydrate as precursor solutions. The solution- processed IZO TFTs showed good performance: a field-effect mobility of $7.29cm^2/Vs$, a threshold voltage of 4.66 V, a subthreshold slope of 0.48 V/dec, and a current on-to-off ratio of $1.62{\times}10^5$. To investigate the static response of our solution-processed IZO TFTs, simple resistor load-type inverters were fabricated by connecting a $2-M{\Omega}$ resistor. Our IZOTFTbased N-MOS inverter performed well at operating voltage, and therefore, isa good candidate for advanced logic circuits and display backplane.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.118-120
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• 2022

This paper investigated the change of threshold voltage according to the influence of work-function variation (WFV) of metal gate in the device structure of monolithic 3-dimension inverter (M3DINV). In addition, in order to investigate the change in threshold voltage according to the electrical coupling of the NMOS stacked on the PMOS, the gate voltages of PMOS were applied as 0 and 1 V and then the electrical coupling was investigated. The average change in threshold voltage was measured to be 0.1684 V, and they standard deviation was 0.00079 V.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.3
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• pp.422-426
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• 2012

Transient radiation is emitted during a nuclear explosion. Transient radiation causes a fatal error in the CMOS circuit as a Upset and Latch-up. In this paper, transient radiation NMOS, PMOS, INVERTER SPICE model was proposed on the basisi of transient radiation effects analysis using TCAD(Technology Computer Aided Design). Photocurrent generated from the MOSFET internal PN junction was expressed to the current source and Latch-up phenomenon in the INVERTER was expressed to parasitic thyristor for the transient radiation SPICE model. For example, the proposed transient radiation SPICE model was applied to CMOS NAND circuit. SPICE simulated characteristics were similar to the TCAD simulation results. Simulation time was reduced to 120 times compared to TCAD simulation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.4
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• pp.76-83
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• 1985

Mo2N/Mo double layer which is to be used for gate of the RMOS (refractory metal oxide semiconductor) and interconnection material has been formed by means of low temperature r.f. reactive sputtering in Ar and N2 mixture. The sheet .esistance of 1 000$\AA$Mo2 N/4000$\AA$Mofilm was about 1.20-1.28 ohms/square, which is about an order of magnitude lower than that of polysilicon film. The workfunction difference naE between MO2N/MO layer and (100) p-Si with 6-9 ohm'cm resistivity obtained from C-V plots was about -0.30ev, and the fixed charge density Qss/q in the oxide was about 2. Ix1011/cm2. To evaluate the signal transfer delay time per inverter stage, an integrated ring oscillator circuit consisting of 45-stage inverters was fabricated using the polysilicon gate NMOS process. The signal transfer delay time per inverter stage obtained in this experiment was about 0.8 nsec

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.9-14
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• 2009

In this paper, we proposed a novel OTP unit bit of CMOS gate oxide antifuse using the standard CMOS process without additional process. The proposed OTP unit bit is composed of 3 transistors including an NMOS gate oxide antifuse and a sense amplifier of inverter type. The layout area of the proposed OTP unit bit is $22{\mu}m^2$ similar to a conventional OTP unit bit. The programming time of the proposed OTP unit bit is 3.6msec that is improved than that of the conventional OTP unit bit because it doesn't use high voltage blocking elements such as high voltage blocking switch transistor and resistor. And the OTP array with the proposed OTP unit bit doesn't need sense amplifier and bias generation circuit that are used in a conventional OTP array because sense amplifier of inverter type is included to the proposed OTP unit bit.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.200-201
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• 2017

This paper introduces the SPICE simulation results of 3D sequential inverter considering electrical coupling. TCAD data and the SPICE data are compared to verify that the electrical coupling is well considered by using BSIM-IMG for the upper NMOS and LETI-UTSOI model for the lower PMOS. When inter layer dielectric is small, it is confirmed that electrical coupling is well reflected in the top transistor $I_{ds}-V_{gs}$ characteristics according to the change of the bottom transistor gate voltage.