• Journal of applied mathematics & informatics
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• 제39권5_6호
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• pp.859-882
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• 2021

In the proposed paper, a new algorithm based on Nonlinear Feedback Shift Register (NLFSR) and modified RC4A (Rivest Cipher 4A) cipher is introduced. NLFSR is used for image pixel scrambling while modified RC4A algorithm is used for pixel substitution. NLFSR used in this algorithm is of order 27 with maximum period 2^27-1 which was found using Field Programmable Gate Arrays (FPGA), a searching method. Modified RC4A algorithm is the modification of RC4A and is modified by introducing non-linear rotation operator in the Key Scheduling Algorithm (KSA) of RC4A cipher. Analysis of occlusion attack (up to 62.5% pixels), noise (salt and pepper, Poisson) attack and key sensitivity are performed to assess the concreteness of the proposed method. Also, some statistical and security analyses are evaluated on various images of different size to empirically assess the robustness of the proposed scheme.

• 대한전자공학회논문지
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• 제24권5호
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• pp.896-904
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• 1987

In this paper, a design method for sequential circuit which is easy to have Built-in Self Test is kproposed using the functional advantages of multifunctional BILBO and LSSD. To achieve the hardware reduction, it is designed that a multifunctional BILBO has double operational functions of NLFSR and LFSR, when neccessary, and that test signal could be used as an input-output signal in the same line. By applying the proposed multifunctional BILBO to the sequential PLA, the test patterns and the additional circuit could be reduced in test operation and the propagation delay is vanished in normal operation, as we expected. Above them, the partitioned method for large scale sequential circuit is also suggested and it is observed that test patterns and additional circuit in them reduced by this method.

• 한국정보통신학회논문지
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• 제11권9호
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• pp.1702-1708
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• 2007

Dragon 스트림 암호 알고리즘은 현재 ECRYPT 프로젝트의 일부인 eSTREAM에 참여하여 소프트웨어 분야(Profile 1)의 Phase 1, 2단계를 통과하여 Phase 3단계에 등록된 상태이다. Dragon은 기존의 스트림 암호와 달리 한 개의 워드(32비트)단위의 NLFSR(non-linear feedback shift register)을 사용하고, 128/256 비트의 key와 IV(Initialization Vector)를 입력받아 64비트의 키 수열을 생성하는 키 수열 발생기(Keystream Generator)이다. 본 논문에서는 Dragon 스트림 암호 알고리즘을 Altera사의 Quartus II툴을 이용하여 Cyclone III FPGA 소자(EP2C35F672I8)에 구현 및 타이밍 시뮬레이션을 하였고, 그 결과 111MHz에서 7.1Gbps의 처리량을 보였다.