• ETRI Journal
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• v.30 no.6
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• pp.856-858
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• 2008

Odd networks were introduced in the context of graph theory. However, their potential as fault-tolerant multiprocessor networks has been shown. Broadcasting is one of the most important communication primitives used in multiprocessor networks. In this letter, we introduce efficient one-to-all broadcasting schemes of odd networks for one-port and all-port models. We show the broadcasting time of the former is 2d-2 and that of the latter is d-1. The total time steps taken by the proposed algorithms are optimal.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10a
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• pp.851-856
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• 1987

A direct computation algorithm of two dimensional fast Fourier transform (2D-FFT) is considered here for implementation in mesh connected multiprocessor array of both a 2D-toroidal and a rectangular type. Results are derived for a hardware algorithm including data allocation and interprocessor communications. A performance comparison is carried out between the proposed direct 2D-FFT computation and the conventional one to show that a new algorithm gives higher speedup under a reasonable assumption on the speeds of operations.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.8
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• pp.927-936
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• 1988

This paper proposes a pipelined memory access method as a new technique for a bus interface between processors and memories in tightly coupled multiprocessor systems. Since the shared bus is bottle neck of the system, model of pipelined access to memory has been developed. Results of the evaluation by the discrete time Markov model showed a significant improvement of the efficiency.

• 제어로봇시스템학회:학술대회논문집
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• 1988.10a
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• pp.407-413
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• 1988

The architecture of a multiprocessor based programmable controller(MBPC) is presented. It consists of a host processor, processing elements, and Input/Output processors. Some problems in implementing such architecture are also described. To resolve them, we proposed and presented INFOBUS, a system bus for MBPC. The performances of INFOBUS and MBPC are analysed using both analytic models and simulations. Some results from the analysis will be given and validated. In case of 50% of BTI(Block Type Instruction) and 4 processors, the scanning time is shown to be 0.194msec/Kstep with some reasonable assumptions.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.430-433
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• 1999

Woo[8]proposed dual-token based fault-tolerant scheduling algorithm in multiprocessor environment for resolving the problem of old systems that have a central dispatcher processor. However, this algorithm does not present token allocation algorithm in detail when central dispatcher processor has failed. In this paper, we propose a fault detection algorithm and processor selection algorithm for token allocation when central dispatcher processor has failed.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10b
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• pp.407-412
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• 1987

A large scale programmable controller is developed which adopts a multiprocessor structure. The developed programmable controller consists of the programmer, the system controller, and the input-output unit. The structure and characteristics of the system controller will be described. The PC has a special hardware scheme to solve the Boolean logic instructions of the sequence control programs. The multiprocessor structure and the special hardware enables, the real time operation and the high speed scanning which is prerequisite to the large scale, programmable controller even for many I/O points.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.37 no.9
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• pp.663-670
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• 1988

Advances in VLSI technology have made it possible to have a larger number of processing elements to be included in highly parallel processor system. A system with a large number of processing elements and memory requires a complex data path. Multistage Interconnection networks(MINS) are useful in providing programmable data path between processing elements and memory modules in multiprocessor system. In this thesis, the performance of MINS for the star network has been analyzed and compared with other networks, such as generalized shuffle network, delta network, and referenced crossbar network.

• Journal of Korean Electronics
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• v.7 no.5
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• pp.27-36
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• 1987

• 전기의세계
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• v.33 no.9
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• pp.557-561
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• 1984

• Journal of Korean Electronics
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• v.7 no.4
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• pp.30-34
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• 1987