• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.59-67
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• 2016

With the enhancement of built-in communication capabilities in various meters and wearable devices, which implies Internet of things (IoT), the demand of small-area embedded processors has increased. In this paper, we introduce a small-area 32-bit pipelined processor, Juno, which is available in the field of IoT. Juno is an EISC (Extendable Instruction Set Computer) machine and has a 2/3-stage pipeline structure to reduce the data dependency of the pipeline. It has a simple pipeline controller which only controls the program counter (PC) and two pipeline registers. It offers $32{\times}32=64$ multiplication, 64/32=32 division, $32{\times}32+64=64$ MAC (multiply and accumulate) operations together with 32*32=64 Galois field multiplication operation for encryption processing in wireless communications. It provides selective inclusion of these algebraic logic blocks if necessary in order to reduce the area of the overall processor. In this case, the gate count of our integer core amounts to 12k~22k and has a performance of 0.57 DMIPS/MHz and 1.024 Coremark/MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.

• The Journal of the Acoustical Society of Korea
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• v.39 no.5
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• pp.441-446
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• 2020

In this paper, we propose the α-Feature Map Scaling (α-FMS) method which extends the FMS method that was designed to enhance the discriminative power of feature maps of deep neural networks in Speaker Verification (SV) systems. The FMS derives a scale vector from a feature map and then adds or multiplies them to the features, or sequentially apply both operations. However, the FMS method not only uses an identical scale vector for both addition and multiplication, but also has a limitation that it can only add a value between zero and one in case of addition. In this study, to overcome these limitations, we propose α-FMS to add a trainable parameter α to the feature map element-wise, and then multiply a scale vector. We compare the performance of the two methods: the one where α is a scalar, and the other where it is a vector. Both α-FMS methods are applied after each residual block of the deep neural network. The proposed system using the α-FMS methods are trained using the RawNet2 and tested using the VoxCeleb1 evaluation set. The result demonstrates an equal error rate of 2.47 % and 2.31 % for the two α-FMS methods respectively.

• The Journal of Society for e-Business Studies
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• v.20 no.3
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• pp.47-58
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• 2015

Recently, new information security vulnerabilities have proliferated with the convergence of information security environments and information and communication technology. Accordingly, new types of cybercrime are on the rise, and security breaches and other security-related incidents are increasing rapidly because of security problems like external cyberattacks, leakage by insiders, etc. These threats will continue to multiply as industry and technology converge. Thus, the main purpose of this paper is to design and present security subjects in order to train professional security management talent who can deal with the enhanced threat to information. To achieve this, the study first set key information security topics for business settings on the basis of an analysis of preceding studies and the results of a meeting of an expert committee. The information security curriculum taxonomy is developed with reference to an information security job taxonomy for domestic conditions in South Korea. The results of this study are expected to help train skilled security talent who can address new security threats in the future environment of industrial convergence.

• Journal of Korea Society of Industrial Information Systems
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• v.14 no.3
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• pp.15-21
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• 2009

In this paper, we proposed an iterative digital image watermarking technique using encrypted binary phase computer generated hologram in the discrete cosine transform(OCT) domain. For the embedding process of watermark, using simulated annealing algorithm, we would generate a binary phase computer generated hologram(BPCGH) which can reconstruct hidden image perfectly instead of hidden image and repeat the hologram and encrypt it through the XOR operation with key image that is ramdomly generated binary phase components. We multiply the encrypted watermark by the weight function and embed it into the DC coefficients in the DCT domain of host image and an inverse DCT is performed. For the extracting process of watermark, we compare the DC coefficients of watermarked image and original host image in the DCT domain and dividing it by the weight function and decrypt it using XOR operation with key image. And we recover the hidden image by inverse Fourier transforming the decrypted watermark. Finally, we compute the correlation between the original hidden image and recovered hidden image to determine if a watermark exits in the host image. The proposed watermarking technique use the hologram information of hidden image which consist of binary values and encryption technique so it is very secure and robust to the external attacks such as compression, noises and cropping. We confirmed the advantages of the proposed watermarking technique through the computer simulations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1218-1226
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• 2008

With the development of semiconductor integrated technology and with the increasing use of multimedia functions in computer, more functions have been implemented as hardware. Nowadays, most microprocessors beyond 32 bits generally implement an integer multiplier as hardware. However, as for a divider, only specific microprocessor implements traditional SRT algorithm as hardware due to complexity of implementation and slow speed. This paper suggested an algorithm that uses a multiplier, 'w bit $\times$ w bit = 2w bit', to process $\frac{N}{D}$ integer division. That is, the reciprocal number D is first calculated, and then multiply dividend N to process integer division. In this paper, when the divisor D is '$D=0.d{\times}2^L$, 0.5 < 0.d < 1.0', approximate value of ' $\frac{1}{D}$', '$1.g{\times}2^{-L}$', which satisfies ' $0.d{\times}1.g=1+e$, $e<2^{-w}$', is defined as over reciprocal number and then an algorithm for over reciprocal number is suggested. This algorithm multiplies over reciprocal number '$01.g{\times}2^{-L}$' by dividend N to process $\frac{N}{D}$ integer division. The algorithm suggested in this paper doesn't require additional revision, because it can calculate correct reciprocal number. In addition, this algorithm uses only multiplier, so additional hardware for division is not required to implement microprocessor. Also, it shows faster speed than the conventional SRT algorithm and performs operation by word unit, accordingly it is more suitable to make compiler than the existing division algorithm. In conclusion, results from this study could be used widely for implementation SOC(System on Chip) and etc. which has been restricted to microprocessor and size of the hardware.

• (The)Study of the Eastern Classic
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• no.73
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• pp.9-33
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• 2018

This paper examines the literary theory of Gollyun(昆侖) Choe, Changdae(崔昌大, 1669-1720). He has authored a variety of works, and his works have been recognized in many literatures. Because of this, studying his literature is a meaningful. The theory of poem creation is as follows. It is the basic poem creationism that expresses the feelings that I experienced and felt as it is. The utility is to multiply and control the artist's feelings through his poem. However, the creative theory of being the best writer is different from this. It must be premised on finding from the heart and studying various books. If these qualities was provided, the words are clear and the meaning is condensed. He distinguished between general works and the best works, and presented their own creative theory and discussed their utility. The theory of prose utility is as follows. He emphasizes the importance of communicating with contemporaries and establishing important things of the day and making them easier to understand, without specifying the morality. This is a thoroughly realistic utility theory. In the classical chinese prose's history, 'Sadal(辭達)' and 'Susa(修辭)' were issues. He transcends the recognition of 'Sadal(辭達)' and 'Susa(修辭)' as zero-sum. In addition, he gives priority to the meaning of the writer and emphasizes self-realization, which is in common with other political soron(少論) writers' theories. When creating prose, simplicity and bizarreness were issues. He emphasizes concise writing. However, it can be realized when a writer with high opinion is aware of the reason and raises the core. Through various sources, he has completely rejected Ming(明) dynasty's former and latter seven master(前後七子). However, he did not exclude their work unilaterally, and recognized the work of Chin-Han dynasty(秦漢) and Dang-Song dynasty(唐宋). This is the same as his father Choiseokjung(崔錫鼎). He recognized Chin-Han dynasty(秦漢) and Dang-Song dynasty(唐宋) equally, and sought a simplified and summarized style.