• Title/Summary/Keyword: Multiplier Generator

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Development of liquid target for beam-target neutron source & two-channel prototype ITER vacuum ultraviolet spectrometer

  • Ahn, B.N.;Lee, Y.M.;Dang, J.J.;Hwang, Y.S.;Seon, C.R.;Lee, H.G.;Biel, W.;Barnsley, R.;Kim, D.E.;Kim, J.G.
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.02a
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    • pp.421-422
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    • 2011
  • The first part is about development of a liquid target for a neutron source, which is designed to overcome many of the limitations of traditional beam-target neutron generators by utilizing a liquid target neutron source. One of the most critical aspects of the beam-target neutron generator is the target integrity under the beam exposure. A liquid target can be a good solution to overcome damage to the target such as target erosion and depletion of hydrogen isotopes in the active layer, especially for the one operating at high neutron fluxes with no need for water cooling. There is no inherent target lifetime for the liquid target neutron generator when used with continuous refreshment of the target surface exposed to the energetic beam. In this work, liquid target containing hydrogen has been developed and tested in vacuum environment. Potentially, liquid targets could allow a point neutron source whose spatial extension is on the order of 1 to $10{\mu}m$. And the second is about the vacuum ultraviolet (VUV) spectrometer which is designed as a five-channel spectral system for ITER main plasma measurement. To develop and verify the design, a two-channel prototype system was fabricated with No. 3 (14.4 nm~31.8 nm) and No. 4 (29.0 nm~60.0 nm) among the five channels. For test of the prototype system, a hollow cathode lamp is used as a light source. The system is composed of a collimating mirror to collect the light from source to slit, and two holographic diffraction gratings with toroidal geometry to diffract and also to collimate the light from the common slit to detectors. The two gratings are positioned at different optical distances and heights as designed. To study the appropriate detector for ITER VUV system, two different electronic detectors of the back-illuminated charge coupled device and the micro-channel plate electron multiplier were installed and the performance has been investigated and compared in the same experimental conditions. The overall system performance was verified by measuring the spectrums.

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Analysis on Spectral Regrowth of Bandwidth Expansion Module by Quadrature Modulation Error in Digital Chirp Generator (디지털 첩 발생기에서의 직교 변조 오차에 의한 대역 확장 모듈에서의 스펙트럴 재성장 분석)

  • Kim, Se-Young;Sung, Jin-Bong;Lee, Jong-Hwan;Yi, Dong-Woo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.7
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    • pp.761-768
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    • 2010
  • This paper presents an effective method to achieve the wideband waveform for high resolution SAR(Synthetic Aperture Radar) using the frequency multiplication technique. And also this paper analyzes the root causes for the spectral regrowth due to 3rd-order intermodulation in chirp bandwidth expansion scheme using quadrature modulator and frequency multipliers. The amplitude and phase imbalance requirement are defined based on the simulation results in terms of quadrature channel imbalance. This minimizes the degradation of range resolution, peak sidelobe ratio and integrated sidelobe ratio. The wideband chirp generator using the frequency multiplier and memory map scheme was manufactured and the compensation technique was presented to reduce the spectral regrowth of SAR waveform by minimizing the amplitude and phase imbalance. After I and Q channel imbalance adjustment, the carrier level reduces -28.7 dBm to -53.4 dBm. Chirp signal with 150 MHz bandwidth at S-band expands to 600 MHz bandwidth at X-band. The sidelobe levels are reduced by about 8 to 9 dB by compensating the amplitude balance between I and Q channels.

90/150 RCA Corresponding to Maximum Weight Polynomial with degree 2n (2n 차 최대무게 다항식에 대응하는 90/150 RCA)

  • Choi, Un-Sook;Cho, Sung-Jin
    • The Journal of the Korea institute of electronic communication sciences
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    • v.13 no.4
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    • pp.819-826
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    • 2018
  • The generalized Hamming weight is one of the important parameters of the linear code. It determines the performance of the code when the linear codes are applied to a cryptographic system. In addition, when the block code is decoded by soft decision using the lattice diagram, it becomes a measure for evaluating the state complexity required for the implementation. In particular, a bit-parallel multiplier on finite fields based on trinomials have been studied. Cellular automata(CA) has superior randomness over LFSR due to its ability to update its state simultaneously by local interaction. In this paper, we deal with the efficient synthesis of the pseudo random number generator, which is one of the important factors in the design of effective cryptosystem. We analyze the property of the characteristic polynomial of the simple 90/150 transition rule block, and propose a synthesis algorithm of the reversible 90/150 CA corresponding to the trinomials $x^2^n+x^{2^n-1}+1$($n{\geq}2$) and the 90/150 reversible CA(RCA) corresponding to the maximum weight polynomial with $2^n$ degree by using this rule block.

A Security SoC embedded with ECDSA Hardware Accelerator (ECDSA 하드웨어 가속기가 내장된 보안 SoC)

  • Jeong, Young-Su;Kim, Min-Ju;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.7
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    • pp.1071-1077
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    • 2022
  • A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.