• Journal of Advanced Marine Engineering and Technology
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• 제26권3호
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• pp.313-319
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• 2002

Since the oil crisis in 1970, a great deal of effort has been made to develop automatic electric load sharing systems as a part of the efforts to save energy. A large scale electric generating system composes more than two generators whose characteristics may be different. When such a system is operated individually or in parallel, the lagrange multiplier's method has difficulty in achieving optimal load distribution because generators usually have the limitations of the operating range with inequality constraints. Therefore, a suitable operating mode of generators has to be decided according to the selection of the generators to meet electric power requirements at the minimum cost. In this study, a method which solves the optimal electric load distribution problem using the dynamic programming technique is proposed. This study also shows that the dynamic programming method has an advantage in dealing with the optimal load distribution problem under the limitations of the operating range with inequality constraints including generator operation mode. In this study, generator operating cost curve of second order equation by shop trial test results of diesel generators are used. The results indicate that the proposed method can be applied to the ship's electric generating system.

• The Transactions of The Korean Institute of Electrical Engineers
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• 제64권8호
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• pp.1212-1216
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• 2015

In this paper, we compared the performance of the Right Handed Nonlinear Transmission Line (RH-NLTL) and Left Handed Nonlinear Transmission Line (LH-NLTL) as a harmonic generator. For a performance comparison, we fabricated both a RH-NLTL and a LH-NLTL harmonic generator whose operational bandwidth is from 0.5 GHz to 1.5 GHz. Under the each condition for the RH-NLTL and the LH-NLTL to maximize second harmonic, the output power of the second harmonic was 9.33 dB lower than the input power for the RH-NLTL and 12.67 dB lower than the input power for the LH-NLTL. Under the each condition for the RH-NLTL and the LH-NLTL to maximize third harmonic, the output power of the third harmonic was 13.33 dB lower than the input power for the RH-NLTL and 14.83dB lower than the input power for the LH-NLTL. Also, we have observed that, generatlly, a RH-NLTL is useful in generating various multiple harmonics and a LH-NLTL is useful in generating a specific order of harmonic by adjusting a proper DC vias, input frequency and input power. These tendencies could be a good guideline to use NLTLs as a frequency multiplier.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제44권9호
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• pp.48-53
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• 2007

Some digital signal processing applications, such as FFT, request multiplications with a group(or, groups) of a few predetermined coefficients. In this paper, based on the modified CSD algorithm, an efficient multiplier design method for predetermined coefficient groups is proposed. In the multiplier design for sine-cosine generator used in direct digital frequency synthesizer(DDFS), and in the multiplier design used in 128 point $radix-2^4$ FFT, it is shown that the area, power and delay time can be reduced up to 34%.

• Journal of the Korean Institute of Telematics and Electronics
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• 제27권4호
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• pp.513-519
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• 1990

In order to realize an efficient and stable X-band harmonic generator, a 100 MHz frequency multiplier, an impulse generator using SRD(Step Recovery Diode) module, and a narrow-band bandpass waveguide filter have been designed and tested. By properly combining these devices an X-band harmonic generator has been realized. The output power of the harmonic generator was measured to be -1.5 dBm at 9 GHz which is the 90th harmonic of the 100MHz input. The power fluctuation of the harmonic generator due to temperature variation was observed to the about 0.15 dB during 24 hours of 4\ulcorner temperature variation.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제12권7호
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• pp.1209-1217
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• 2008

In this paper, we present a new bit-parallel multiplier for performing the bit-parallel multiplication of two polynomials in the finite fields $GF(2^m)$. Prior to construct the multiplier circuits, we consist of the vector code generator(VCG) to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial after performing the parallel multiplication of a multiplicand polynomial with a irreducible polynomial. The basic cells of VCG have two AND gates and two XOR gates. Using these VCG, we can obtain the multiplication results performing the bit-parallel multiplication of two polynomials. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields $GF(2^4)$. Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper use the VCGs with the basic cells repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSI.

• Proceedings of the KIEE Conference
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 B
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• pp.778-780
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• 1999

Arithmetic unit speed depends strongly on the algorithms employed to realize the basic arithmetic operations.(add, subtract multiply, and divide) and on the logic design. Recent advances in VLSI have increased the feasibility of hardware implementation of floating point arithmetic units and microprocessors require a powerful floating-point processing unit as a standard option. This paper describes the design of floating-point multiplier for IEEE 754-1985 Single-Precision operation. Booth encoding algorithm method to reduce partial products and a Wallace tree of 4-2 CSA is adopted in fraction multiplication part to generate the $32{\times}32$ single-precision product. New scheme of rounding and sticky-bit generation is adopted to reduce area and timing. Also there is a true sign generator in this design. This multiplier have been implemented in a ALTERA FLEX EPF10K70RC240-4.

• Proceedings of the KIPE Conference
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• 전력전자학회 2020년도 전력전자학술대회
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• pp.397-398
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• 2020

최근 COVID-19(Coronavirus disease, 2019)의 발병으로 정확한 진단을 하기위한 X-ray 검사에 대한 수요가 증가하고 있다. 품질이 높은 수준의 Xray 영상을 얻기 위해서는 X-ray 튜브에 촬영 목적에 맞는 일정한 고전압을 제어를 통해 인가해야 한다. 그러기 위해서는 전력변환장치의 출력전압 특성을 고려하여 설계해야 한다. 따라서 Xray 발생장치에 주로 사용되는 Cockcroft-Walton Voltage Multiplier를 사용하여 다이오드의 기생커패시턴스 성분이 변압기의 누설 인덕턴스 성분, 회로의 기생 인덕턴스 성분과 공진현상을 일으켜 발생하는 출력전압의 특성 변화에 대한 시뮬레이션을 개발하고 분석 하였다.

• Journal of Advanced Marine Engineering and Technology
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• 제23권2호
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• pp.210-215
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• 1999

The proposed detector is consists of three-phase sinusoidal signal generator and peak detector. This peak detector can detect the peak voltage value at the state of variable frequency. In experi-ment three-phase sinusoidal signals are generated from D/A converter using IBM PC and deliv-ered to the peak detector. Each signals are squared by multiplier and summed up Peak value is the square root of summed value extracted by square root circuit.

• Journal of IKEEE
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• 제9권1호
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• pp.1-6
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• 2005

This paper proposes a high performance multiplier using CMOS multiple-valued logic circuits. The multiplier based on the Modified Baugh-Wooley algorithm is designed with current-mode CMOS quaternary logic circuits. The multiplier is functionally partitioned into the following major sections: partial product generator block(binary-quaternary logic conversion block), current-mode quaternary logic full-adder block, and quaternary-binary logic conversion block. The proposed multiplier has 4.5ns of propagation delay and 6.1mW of power consumption. This multiplier can easily adapted to the binary system by the encoder and the decoder. This circuit is designed with 0.35um standard CMOS process at 3.3V supply voltage and 5uA unit current. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of Korea Society of Industrial Information Systems
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• 제18권5호
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• pp.9-14
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• 2013

This paper is designed frequency multiplier with low phase noise using DLL technique. The VCDL is designed using a differential structure to reduce common-mode noise. The proposed frequency multiplier is fabricated in a 65nm, 1.2V TSMC CMOS process, and the operating frequency range from 10MHz to 24MHz was measured. The SSB phase noise is measured to be -125dBc/Hz at 1MHz from 38.4MHz carrier. A total area of $0.032mm^2$were consumed in the chip, including the output buffer. Total current is 1.8mA at 1.2V supply voltage.