• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.123-130
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• 2004

This paper describes a multiplier architecture optimized for 32 bit RISC processor with 3-stage pipeline. The multiplier of ARM7, the target processor, is variably carried out on the execution stage of pipeline within 7 cycles. The included multiplier employs a modified Booth's algerian to produce 64 bit multiplication and addition product and it has 6 separate instructions. We analyzed several multiplication algorithm such as radix4-32${\times}$8, radix4-32${\times}$16 and radix8-32${\times}$32 to decide which multiplication architecture is most fit for a typical architecture of ARM7. VLSI area, cycle delay time and execution cycle number is the index of an efficient design and the final multiplier was designed on these indexes. To verify the operation of embedded multiplier, it was simulated with various audio algorithms.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.10
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• pp.1216-1224
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• 1988

In this paper, it is presented element generation, addition, multiplication and division algorithm over GF ($2^m$) to calculate multiple-valued logic function. The results of addition and multiplication among these algorithms are applied to the current mode CMOS circuits with ROM structure to design of adder and multiplier on GF ($2^m$). Table-lookup and Euclid's algorithm are required the computation in large quentities when multiple-valued logic functions are developed on GF ($2^m$). On the contrary the presented operation algorithms are prefered to the conventional methods since they are processed without relation to increasing degree m in the general purpose computer. Also, the presened logic circuits are suited for the circuit design of the symmetric multiplevalued truth-tables and they can be implemented addition and multiplication on GF ($2^m$) simultaueously.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.190-192
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• 2018

This paper describes a design of an elliptic curve cryptography (ECC) processor that supports five pseudo-random curves and five Koblitz curves over binary field defined by the NIST standard. The ECC processor adopts the Lopez-Dahab projective coordinate system so that scalar multiplication is computed with modular multiplier and XORs. A word-based Montgomery multiplier of $32-b{\times}32-b$ was designed to implement ECCs of various key lengths using fixed-size hardware. The hardware operation of the ECC processor was verified by FPGA implementation. The ECC processor synthesized using a 0.18-um CMOS cell library occupies 10,674 gate equivalents (GEs) and 9 Kbits RAM at 100 MHz, and the estimated maximum clock frequency is 154 MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.1C
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• pp.131-139
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• 2008

This paper presents a scalable dual-field Montgomery multiplier based on a new multi-precision carry save adder(MP-CSA), which operates in both types of finite fields GF(p) and GF($2^m$). The new MP-CSA consists of two carry save adders(CSA). Each CSA is composed of n = [w/b] carry propagation adders(CPA) for a modular multiplication with w-bit words, where b is the number of dual field adders(DFA) in a CPA. The proposed Montgomery multiplier has roughly the same timing complexity compared with the previous result, however, it has the advantage of reduced chip area requirements. In addition, the proposed circuit produces the exact modular multiplication result at the end of operation unlike the previous architecture. Furthermore, the proposed Montgomery multiplier has a high scalability in terms of w and m. Therefore, it can be used to multiplier over GF(p) and GF($2^m$) for cryptographic applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1836-1842
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• 2010

Sensor network, which is technology to realize the ubiquitous environment, recently, could apply to the field of Mechanic & electronic Security System, Energy management system, Environment monitoring system, Home automation and health care application. However, feature of wireless networking of sensor network is vulnerable to eavesdropping and falsification about message. Presently, PKC(public key cryptography) technique using ECC(elliptic curve cryptography) is used to build up the secure networking over sensor network. ECC is more suitable to sensor having restricted performance than RSA, because it offers equal strength using small size of key. But, for high computation cost, ECC needs to enhance the performance to implement over sensor. In this paper, we propose the optimizing technique for multiplication, core operation in ECC, to accelerate the speed of ECC.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.10
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• pp.1403-1408
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• 2021

Recently, FPGA-based AI processors are being studied actively. Deep convolutional neural networks (CNN) are basic computational structures performed by AI processors and require a very large amount of multiplication. Considering that the multiplication coefficients used in CNN inference operation are all constants and that an FPGA is easy to design a multiplier tailored to a specific coefficient, this paper proposes a methodology to optimize the multiplier. The method utilizes 2's complement and distributive law to minimize the number of bits with a value of 1 in a multiplication coefficient, and thereby reduces the number of required stacked adders. As a result of applying this method to the actual example of implementing CNN in FPGA, the logic usage is reduced by up to 30.2% and the propagation delay is also reduced by up to 22%. Even when implemented with an ASIC chip, the hardware area is reduced by up to 35% and the delay is reduced by up to 19.2%.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.3
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• pp.41-48
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• 2004

Finite field multiplication and division are important arithmetic operation in error-correcting codes and cryptosystems. The elements of the finite field GF($2^m$) are represented by bases with a primitive polynomial of degree m over GF(2). We can be easily realized for multiplication or computing multiplicative inverse in GF($2^m$) based on a normal basis representation. The number of product terms of logic function determines a complexity of the Messay-Omura multiplier. A normal basis exists for every finite field. It is not easy to find the optimal normal element for a given primitive polynomial. In this paper, the generating method of normal basis is investigated. The normal bases whose product terms are less than other bases for multiplication in GF($2^m$) are found. For each primitive polynomial, a list of normal elements and number of product terms are presented.

• International Journal of Internet, Broadcasting and Communication
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• v.16 no.1
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• pp.17-28
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• 2024

As listed as one of the most important requirements for Post-Quantum Cryptography standardization process by National Institute of Standards and Technology, the resistance to various side-channel attacks is considered very critical in deploying cryptosystems in practice. In fact, cryptosystems can easily be broken by side-channel attacks, even though they are considered to be secure in the mathematical point of view. The timing attack(TA) and the simple power analysis attack(SPA) are such side-channel attack methods which can reveal sensitive information by analyzing the timing behavior or the power consumption pattern of cryptographic operations. Thus, appropriate measures against such attacks must carefully be considered in the early stage of cryptosystem's implementation process. The Montgomery multiplier is a commonly used and classical gadget in implementing big-number-based cryptosystems including RSA and ECC. And, as recently proposed as an alternative of building blocks for implementing post quantum cryptography such as lattice-based cryptography, the big-number multiplier including the Montgomery multiplier still plays a role in modern cryptography. However, in spite of its effectiveness and wide-adoption, the multiplier is known to be vulnerable to TA and SPA. And this paper proposes a new countermeasure for the Montgomery multiplier against TA and SPA. Briefly speaking, the new measure first represents a multiplication operand without 0 digits, so the resulting multiplication operation behaves in a very regular manner. Also, the new algorithm removes the extra final reduction (which is intrinsic to the modular multiplication) to make the resulting multiplier more timing-independent. Consequently, the resulting multiplier operates in constant time so that it totally removes any TA and SPA vulnerabilities. Since the proposed method can process multi bits at a time, implementers can also trade-off the performance with the resource usage to get desirable implementation characteristics.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.32 no.2
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• pp.163-170
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• 2022

LEA is a lightweight block cipher developed in Korea in 2013. In this paper, among block cipher operation methods, CTR operation mode and GCM operation mode that provides confidentiality and integrity are implemented. In the LEA-CTR operation mode, we propose an optimization implementation that omits the operation between states through the state fixation and omits the operation through the pre-operation by utilizing the characteristics of the fixed nonce value of the CTR operation mode. It also shows that the proposed method is applicable to the GCM operation mode, and implements the GCM through the implementation of the GHASH function using the Galois Field(2¹²⁸) multiplication operation. As a result, in the case of LEA-CTR to which the proposed technique is applied on 32-bit RISC-V, it was confirmed that the performance was improved by 2% compared to the previous study. In addition, the performance of the GCM operation mode is presented so that it can be used as a performance indicator in other studies in the future.

• The Transactions of the Korea Information Processing Society
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• v.2 no.6
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• pp.969-973
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• 1995

In this paper, a new parallel Multiplier array is proposed to reduce the multiplication time by modifying CAS(carry select adder) cell structure used in the conventional parallel multiplier array. It is named MCSA(modified CSA) that assignes the addend and augend to the inputs of CSA faster than Ci(carry input). Also the designed DCSA (doubled inverted input CSA) is appended after the last product term for the carry propagation adder. The proposed scheme is designed with MCSA and DCSA, and simulated. It is verified that the circuit size is increased about 13% compared with the conventional multiplier array with CSA cell but the operation time is reduced about 52%.