• 한국컴퓨터산업학회논문지
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• 제2권9호
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• pp.1183-1190
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• 2001

본 논문에서는 아날로그의 비디오 신호를 디지털로 부호화하는데 기존과 다른 파이프라인 방식을 사용하도록 하였다. 부호화기의 전체 동작을 화소 클럭비에 따른 파이프라인 구조로 설계하여 각 하위 블록들의 동작 타이밍을 확보하여 시스템을 안정화시켰으며 고정된 계수와 곱셈의 경우 기존의 ROM 테이블 또는 곱셈기 방식을 사용하지 않고 쉬프트와 덧셈기 방식으로 설계함으로써 시스템의 복잡도를 줄이며 논리 게이트 수를 15%줄이는 효과를 보였다. 설계된 부호화기는 각각의 하위 블록으로 나누어 VHDL로 설계하였고, Max+plusII를 이용한 FPGA로 동작 확인을 하였다.

• 정보처리학회논문지A
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• 제8A권2호
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• pp.125-132
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• 2001

IBM developed the MPI-IO, we call it MPI-2, on the General Parallel File System. We designed and implemented various Matrix Multiplication Benchmarks to evaluate its performances. The MPI-IO on the General Parallel File System shows four kinds of data access methods : the non-collective and blocking, the collective and blocking, the non-collective and non-blocking, and the split collective operation. In this paper, we propose benchmarks to measure the IO time and the computation time for the data access methods. We describe not only its implementation but also the performance evaluation results.

• 한국통신학회논문지
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• 제26권9B호
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• pp.1226-1235
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• 2001

The convergence analysis of the improved multiplication free adaptive digital filter (IMADF) with a fractionally-spaced equalizer (FSE) to remove the intersymbol interference (ISI) in fast data transmission is presented. The IMADF structure use the one-step predicted filter in the multiplication-free adaptive digital filter (MADF) structure using the DPCM and Sign algorithm. In the experimental results, the IMADF algorithm has reduced the computational complexity by use of only the addition operation without a multiplier. Also, under the condition of identical stationary-state error, it could obtain the stabled convergence characteristic that the IMADF algorithm is almost same as the sign algorithm, but is better than the MADF algorithm. Here, this algorithm has effective characteristics when the correlation of the input signal is highly.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2005년도 춘계학술발표대회
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• pp.863-866
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• 2005

Low-power design is one of the most important challenges encountered in maximizing battery life in portable devices as well as saving energy during system operation. In this paper we propose a low-power DCT (Discrete Cosine Transform) architecture using a modified Computation Sharing Multiplication (CSHM). The overall rate of power consume is reduced during DCT: the proposed architecture does not perform arithmetic operations on unnecessary bits during the Computation Sharing Multiplication calculations. Experimental results show that it is possible to reduce power dissipation up to about $7{\sim}8%$ without compromising the final DCT results. The proposed lowpower DCT architecture can be applied to consumer electronics as well as portable multimedia systems requiring high throughput and low-power.

• ETRI Journal
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• 제41권6호
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• pp.863-872
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• 2019

Elliptic curve cryptography is a relatively lightweight public-key cryptography method for key generation and digital signature verification. Some lightweight curves (eg, Curve25519 and Curve Ed448) have been adopted by upcoming Transport Layer Security 1.3 (TLS 1.3) to replace the standardized NIST curves. However, the efficient implementation of Curve Ed448 on Internet of Things (IoT) devices remains underexplored. This study is focused on the optimization of the Curve Ed448 implementation on low-end IoT processors (ie, 8-bit AVR and 16-bit MSP processors). In particular, the three-level and two-level subtractive Karatsuba algorithms are adopted for multi-precision multiplication on AVR and MSP processors, respectively, and two-level Karatsuba routines are employed for multi-precision squaring. For modular reduction and finite field inversion, fast reduction and Fermat-based inversion operations are used to mitigate side-channel vulnerabilities. The scalar multiplication operation using the Montgomery ladder algorithm requires only 103 and 73 M clock cycles on AVR and MSP processors.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.573-574
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• 2006

A low-power power-aware scalable pipelined Booth recoded multiply & Accumulate unit (PA-MAC) detects the input operands for their dynamic range and accordingly implements a 16-bit, 8-bit or 4-bit multiplication and accumulation operation. The multiplication mode is determined by the dynamic - range detection unit. For the computations, although an area of the proposed PA-MAC is lager than a non-scalable MAC respectively, the proposed PA-MAC proves to be globally more power efficient than a non-scalable MAC.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(5)
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• pp.169-172
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• 2001

In this paper, it used a different pipeline method from conventional method which is encoding the video signal of analog with digital. It designed with pipeline structure of 4 phases as the pixel clock ratio of the whole operation of the encoder, and secured the stable operational timing of the each sub-blocks, it was visible the effect which reduces a gate possibility as designing by the ROM table or the shift and adder method which is not used a multiplication flag method of case existing of multiplication of the fixed coefficient. The designed encoder shared with the each sub-block and it designed the FPGA using MAX+PLUS2 with VHDL.

• 전기전자학회논문지
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• 제25권1호
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• pp.174-179
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• 2021

에드워즈 곡선 Edwards25519와 Edwards448 상의 점 스칼라 곱셈(point scalar multiplication; PSM)을 지원하는 EdCC (Edwards curve cryptography) 코어를 설계하였다. 저면적 구현을 위해 워드 기반 몽고메리 곱셈 알고리듬을 기반으로 유한체 곱셈기를 설계하였으며, 나눗셈 연산 없이 점 연산을 구현하기 위해 확장 트위스티드 에드워즈 좌표계를 적용하였다. EdCC 코어를 100 MHz의 클록으로 합성한 결과, 24,073 등가 게이트와 11 kbit의 RAM으로 구현되었으며, 최대 동작 주파수는 285 MHz로 추정되었다. Edwards25519와 Edwards448 곡선 상의 PSM을 각각 초당 299회, 66회 연산하는 것으로 평가되었으며, 유사한 구조의 타원곡선 암호 코어에 비해 256 비트 PSM 연산에 소요되는 클록 사이클 수가 약 60 % 감소하여 연산 성능이 약 7.3 배 향상되었다.

• 전자통신동향분석
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• 제32권6호
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• pp.57-65
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• 2017

Neural network based AI computing is a promising technology that reflects the recognition and decision operation of human beings. Early AI computing processors were composed of GPUs and CPUs; however, the dramatic increment of a floating point operation requires an energy efficient AI processor with a highly parallelized architecture. In this paper, we analyze the trends in processor architectures for AI computing. Some architectures are still composed using GPUs. However, they reduce the size of each processing unit by allowing a half precision operation, and raise the processing unit density. Other architectures concentrate on matrix multiplication, and require the construction of dedicated hardware for a fast vector operation. Finally, we propose our own inAB processor architecture and introduce domestic cutting-edge processor design capabilities.

• 전자공학회논문지SC
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• 제38권1호
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• pp.27-34
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• 2001

[ $GF(2^m)$ ]의 기약 3항식인 $x^m+x+1$을 이용한 승산기 알고리즘은 Mastrovito에 의해 제안되었다. 본 논문에서는 기약 3항식 $x^m+x+1$에서 1$GF(2^m)$상의 원시 기약 3 항식을 전개하여 회로를 간략화 하였으며, 제안된 승산기 설계는 규칙적이며 모듈러 구조, 그리고 간단한 제어신호를 요하기 때문에 VLSI 실현이 용이하다고 사료된다.