• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.4A
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• pp.379-386
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• 2007

In this paper, we propose an efficient diagnosis algorithm for multiple stuck-at faults. Because of using vectorwise intersections as an important metric of diagnosis, the proposed diagnosis algorithm can diagnose multiple defects in single stuck-at fault simulator. In spite of multiple fault diagnosis, the number of candidate faults is drastically reduced. For identifying faults, the variable weight, positive calculations and negative calculations are used for the matching algorithm. To verify our algorithm, experiments were performed for ISCAS85 and full-scan version of ISCAS89 benchmark circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.59-63
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• 2006

With the increasing complexity of VLSI devices, more complex faults have appeared. Many methods for diagnosing the single stuck-at fault have been studied. Often multiple defects on a foiling chip better reflect the reality. So, we propose an efficient diagnosis algorithm for multiple stuck-at faults. By using vectorwise intersections as an important metric of diagnosis, the proposed algorithm can diagnose multiple defects using single stuck-at fault simulator. In spite of multiple fault diagnosis, the number of candidate faults is also drastically reduced. For fault identification, positive calculations and negative calculations based on variable weights are used for the matching algorithm. Experimental results for ISCAS85 and full-scan version of ISCAS89 benchmark circuits prove the efficiency of the proposed algorithm.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.12
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• pp.1552-1564
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• 1995

A fault detecting method of ternary logic is proposed by using the spectral coefficients of the Chrestenson function. Fault detecting conditions are derived for a stuck-at fault in case of single input, multiple inputs and internal lines in the ternary logic. The detecting conditions for min/max bridging faults are also considered. When using this fault analysis method, it is possible to detect faults without the test vector and minimize high volume memory for storing the vector and response data. Thus, the computational complexity for the test vector can be decreased.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.4
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• pp.99-105
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• 1994

k-bounded circuits are combinational circuits proposed by Fujiwara whose subcircuits are partitioned in a way that they form a tree and have some restricted k inputs respectively. Fujiwara proposed a O($16^{k}m$) fault detection algorithm for k-bounded circuits where m is the number of signal lines in the circuit. This algorithm is very ineffective to be applied to real circuits, even for small values of k. In this paper, it is shown that a single stuck-at fault in k-bounded circuits can be detected in O($2^{k}m$)time, and multiple stuck-at faults are detected in O($4^{k}m$) time by using thable lookup and imput partitionsing.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.311-323
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• 1997

This paper presents a fast fault simulation system for detecting stuck-at faults in mixed-level combinational logic circuits with gale level and switch -level primitives. For a practical fault simulator, the types are not restricted to static switch-level and/or gate-level circuits, but include dynamic switch-level circuits. To efficiently handle the multiple signal contention problems at wired logic elements, we propose a six-valued logic system and its logic calculus which are used together with signal strength information. As a basic algorithm for the fault simulation process, a well -known gate-level parallel pattern single fault propagation(PPSFP) technique is extended to switch-level circuits in order to handle pass-transistor circuits and precharged logic circuits as well as static CMOS circuits. Finally, we demonstrate the efficiency of our system through the experimental results for switch-level ISCAS85 benchmark combinational circuits and various industrial mixed-level circuits.