• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1991년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 22-24 Oct. 1991
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• pp.1149-1154
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• 1991

For a robotic workcell, which consists of multiple robots, several interconnection methods are presented in terms of the processor based architecture. Since few attempts have been made to formulate and analyze multiple robot system(MRS), we turn the knowledge of multiple processor system(MPS) or multiple computer system(MCS) to good account. The performance evaluation is achieved through queueing analysis, the aim being to compare their response time, utilization, probability of service failure under different workload. To verify the validity of the proposed analysis methods, a computer simulation is performed. The results together with comments presented here give some useful guidelines for the selection of an appropriate interconnection method.

• 한국통신학회논문지
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• 제32권10C호
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• pp.1025-1031
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• 2007

본 논문에서는 송수신 안테나가 각각 4개인 MIMO-OFDM 시스템을 위한 효율적인 FFT 프로세서 구조를 제안한다. MIMO-OFDM 시스템의 기본은 다중 데이터 패스의 전송이므로 기존의 SISO-OFDM 시스템의 FFT 프로세서를 MIMO-OFDM 시스템에 그대로 적용하면 하드웨어 복잡도가 데이터 패스의 수에 선형적으로 증가하게 된다. 따라서 MIMO-OFDM 시스템에 맞도록 저면적의 다채널 FFT 프로세서가 요구된다. 제안된 FFT 프로세서는 다채널 MDC구조를 갖기 때문에 MIMO-OFDM 시스템의 다중 데이터 패스를 효과적으로 처리할 수 있으며, mixed radix 기법을 통한 효율적인 radix 분해를 이용하여 비단순 승산의 수를 감소시켰다. 제안된 구조를 갖는 FFT 프로세서는 HDL을 사용하여 설계된 후 0.18um CMOS 셀 라이브러리를 이용하여 설계되었다. 논리합성 결과, 4채널 radix-4 Multipath Delay Commutator (R4MDC) FFT 프로세서와 비교시 약 25%의 하드웨어가 감소함을 확인하였다. FFT 프로세서는 전체 MIMO-OFDM 시스템에서 약 30% 정도를 차지하는 커다란 블록이기 때문에, 제안된 FFT프로세서는 MIMO-OFDM 시스템의 하드웨어 복잡도를 감소시키는데 큰 공헌을 할 수 있다.

• Journal of information and communication convergence engineering
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• 제17권1호
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• pp.1-7
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• 2019

In this paper, we present the block diagonalization (BD) algorithm for the multiple-user multiple input multiple output (MU-MIMO) $4{\times}4$ system using specific purpose processor (SPP) hardware. Our objective is to improve the single-user MIMO (SU-MIMO) system using the MU-MIMO technology, which is remarkably fast and allows more users to connect simultaneously. To that end, our MU-MIMO precoder uses the BD algorithm to ensure signal integrity when connecting multiple users; but remains accurate and stable. However, a precoder that uses the BD algorithm is computationally complex; therefore, we use an SPP with special functions designed to compute the BD algorithm. The implementation test results show that our SPP computes the BD algorithm faster than the software solution.

• 한국항행학회논문지
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• 제21권6호
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• pp.659-665
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• 2017

본 논문에서는 MIMO(multiple input multiple output) 시스템을 위한 저복잡도 FFT(fast Fourier transform) 프로세서의 설계 및 구현 결과를 제시하였다. 무선랜을 이용한 다양한 멀티미디어 서비스 등을 이용하기 위해 높은 채널 용량과 Gbps급 전송이 가능한 시스템에 대한 요구와 함께 IEEE 802.11ac 규격이 채택되었다. MIMO-OFDM (orthogonal frequency duplex multiplexing) 기술을 사용하는 IEEE 802.11ac 규격의 무선랜 시스템은 최대 8개의 안테나 구성 및 20-160 MHz 대역폭을 지원해야한다. 따라서, 제안된 FFT 프로세서는 8채널 64, 128, 256, 512 point 가변길이를 지원한다. 또한, 비단순 승산기의 수를 감소시키기 위해서 MRMDC(mixed-radix multipath delay commutator) 구조를 적용하였고, 이로 인해 제안된 FFT 프로세서는 기존 FFT 프로세서에 비해 현저히 낮은 복잡도로 구현 가능하다. 구현 결과, 제안된 FFT processor는 기존 방식인 radix-2 SDF 구조 대비 gate count가 50 % 감소 가능하였고, 8 채널 MR-2/2/2/4/2/4/2 MDC 구조와 8채널 MR-2/2/2/8/8 MDC 구조 대비 logic gate 수를 각각 18 %와 17 % 감소 가능함이 확인되었다.

• International Journal of Aeronautical and Space Sciences
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• 제3권2호
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• pp.31-39
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• 2002

In this paper, KOMPSAT-2 on-board fault and ground recovery management design is addressesed in terms of hardware and software components which provide failure detection and spacecraft safing for anomalies which threaten spacecraft survival. It also includes ground real time up-commanding operation to recover the system safely. KOMPSAT-2 spacecraft fault and recovery management is designed such that the subsequent system configuration due to system initialization is initiated and controlled by processors. This paper will show that KOMPSAT-2 has a new design feature of CPU SEU mitigation for the possible upsets in the processor CPUs as a part of on-board fault management design. Recovery management of processor switching has two different ways: gang switching and individual switching. This paper will show that the difficulties of using multiple-processor system can be managed by proper design implementation and flight operation.

• 한국정보전자통신기술학회논문지
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• 제2권3호
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• pp.39-52
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• 2009

Scale Invariant Feature Transform (SIFT) is an effective algorithm in object recognition, panorama stitching, and image matching, however, due to its complexity, real time processing is difficult to achieve with software approaches. This paper proposes using a reconfigurable hardware processor with integer half kernel. The integer half kernel Gaussian reduces the Gaussian pyramid complexity in about half [] and the reconfigurable processor carries out a parallel implementation of a full search Fast SIFT algorithm. We use a low memory, fine grain single instruction stream multiple data stream (SIMD) pixel processor that is currently being developed. This implementation fully exposes the available parallelism of the SIFT algorithm process and exploits the processing and I/O capabilities of the processor which results in a system that can perform real time image and video compression. We apply this novel implementation to images and measure the effectiveness. Experimental simulation results indicate that the proposed implementation is capable of real time applications.

• 대한전기학회논문지:시스템및제어부문D
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• 제53권6호
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• pp.440-445
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• 2004

The design and implementation of a Network Processor using System-on-a-chip(SoC) technology is presented. The proposed network processor can handle several protocols as well as various types of traffics simultaneously. The proposed SoC consists of ARM processor core, ATM block, AAL processing block, Ethernet block and a scheduler. The scheduler guarantees QoS of the voice traffic and supports multiple AAL2 packet. The SoC is manufactured on the 0.35 micron fabrication line of HYNIX semiconductor, the total number of gates is about 312,000, for a maximum operating frequency of over to 50㎒.

• 전자공학회논문지C
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• 제34C권5호
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• pp.19-32
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• 1997

So far, the multiple path MINs to provide redundant paths in the traditional UPP MINs have been realized by adding additional hardware such as extra stages, duplicated data links, or multiple copies of sthe MIN. And the traditional MINs do not exploit locality: communication with all processor-memory paris takes the same amount of time. Also so far there has been little progress for exploiting locality of reference in MINs. In this paper, we present a new topology MIN, hybrid MIN that is constructed with 2N-3 SEs which is far fewer SEs than that of traditional MINs. Although the hybrid MIN is constructed with 2N-3 SEs, the hybrid MIN satisfies full access capability (FAC) and has redundant paths(but providing single path for 2 memory modules of each processor). Moreover the has redundant paths (but providing single path for 2 memory modules of each processor). Moreover the Hybrid MIN provides shortcut path between pairs which have frequent dat acommunication (locality of reference). Its performance under varing degrees of localized communication is analyzed.

• Journal of Electrical Engineering and information Science
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• 제2권3호
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• pp.105-112
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• 1997

The performance of a shared memory multiprocessor system is very sensitive to process scheduling. w can enhance the performance of a whole system as well as of an individual process by taking the multiprocessor characteristics into account in the design of the process scheduler. In this paper, we proposed a general purpose scheduler for a shared memory multiprocessor, called the Two-Level Multi-Scan (TLMS) process scheduler, that considers the processor affinity loosely and decreases the interference among multiple processors greatly. The TLMS scheduler is composed of a local scheduler at each processor and a semi-global scheduler that balances the load among processors. In particular, the semi-global scheduler tries to minimize priority inversion, which is an important factor of the system performance. The TLMS scheduler also tries to reduce the number of resources to be shared and improves the processor utilization. to meet these requirements, th semi-global scheduler interacts with the operation of the local scheduler when a need arises, thus the name is loose processor-affinity. We also show that the proposed scheduling technique can be extended for other types of resources making it a general purpose resource management queue.

• 대한임베디드공학회논문지
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• 제6권2호
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• pp.100-107
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• 2011

As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements(PEs) and operates on a 3-stage pipelining. Experimental results for the JPEG encoding algorithm indicate that the proposed parallel processor outperforms conventional parallel processors in terms of performance and energy efficiency. In addition, the proposed parallel processor architecture was developed and verified with verilog HDL and a FPGA prototype system.