• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.9
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• pp.1069-1080
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• 2016

TDOA(Time Difference Of Arrival)-based localization system such as the passive surveillance system performs the time synchronization between the receivers after separated installing multiple receivers to set the same clock for all receivers. And it estimates 2D(or 3D) location of the target by solving intersection of the multiple hyperbola(or hyperboloid) using TDOA. To perform time synchronization, one receiver must be set to the master, and it provide the reference data to compensate the clock of the rest of the slaves. The positioning accuracy of TDOA-based localization system is changed in accordance with the master that is selected among multiple receivers. So, the optimum receiver which is selected among multiple receivers must be set to master to get best performance in the considered deployment of receivers. In this paper, we propose a selection scheme of master receiver for time synchronization using DOP(Dilution Of Precision) which is based on location of the target and the multiple receivers. The proposed scheme has low complexity and short processing time, and it is easy to automate in the TDOA-based localization systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.6
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• pp.475-484
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• 1990

This paper proposes a method for the implementation of a power line communication equipment using power line synchronization in a direct-sequence spread spectrum communication system. In order to implement a network using a power line as a transmission channel we have investigated the utilization of direct-sequence speread spctrum which gives such advantages as robustness against narrow-band interference and noise, and realization of multiple access. In a power line, however, complexity of synchronization makes it difficult to realize a multiple access and cost down and system simplification. The proposed technique of power line synchronization makes it possible to get cost down and system size small, and the realization of multiple communication can be achieved by the addition of address setting circuit.

• ETRI Journal
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• v.32 no.2
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• pp.222-229
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• 2010

A conventional pseudorandom sequence generator creates only 1 bit of data per clock cycle. Therefore, it may cause a delay in data communications. In this paper, we propose an efficient implementation method for a pseudorandom sequence generator with parallel outputs. By virtue of the simple matrix multiplications, we derive a well-organized recursive formula and realize a pseudorandom sequence generator with multiple outputs. Experimental results show that, although the total area of the proposed scheme is 3% to 13% larger than that of the existing scheme, our parallel architecture improves the throughput by 2, 4, and 6 times compared with the existing scheme based on a single output. In addition, we apply our approach to a $2{\times}2$ multiple input/multiple output (MIMO) detector targeting the 3rd Generation Partnership Project Long Term Evolution (3GPP LTE) system. Therefore, the throughput of the MIMO detector is significantly enhanced by parallel processing of data communications.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.6
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• pp.1247-1254
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• 2020

With the advent of the smart home era, equipment that provides confidentiality or performs authentication exists in various places in real life. Accordingly security against physical attacks is required for encryption equipment and authentication equipment. In particular, fault injection attack that artificially inject a fault from the outside to recover a secret key or bypass an authentication process is one of the very threatening attack methods. Fault sources used in fault injection attacks include lasers, electromagnetic, voltage glitches, and clock glitches. Fault injection attacks are classified into single fault injection attacks and multiple fault injection attacks according to the number of faults injected. Existing multiple fault injection systems generally use a single fault source. The system configured to inject a single source of fault multiple times has disadvantages that there is a physical delay time and additional equipment is required. In this paper, we propose a multiple fault injection system using heterogeneous fault sources. In addition, to show the effectiveness of the proposed system, the results of a multiple fault injection attack against Riscure's Piñata board are shown.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.629-638
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• 2005

In the System on a Chip design, the on chip bus is one of the critical factors that decides the overall system performance. Especially, in the case or reusing the IPs such as processors, DSPs and multimedia IPs that requires higher bandwidth, the bandwidth problems of on chip bus are getting more serious. Recently ARM proposes the Multi-Layer AHB BusMatrix that is a highly efficient on chip bus to solve the bandwidth problems. The Multi-Layer AHB BusMatrix allows parallel access paths between multiple masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. However, there is one clock cycle delay for each master in existing Multi-Layer AHB BusMatrix whenever the master starts new transactions or changes the slave layers because of the Input Stage and arbitration logic realized with Moore type. In this paper, we improved the existing Multi-Layer AHB BusMatrix architecture to solve the one clock cycle delay problems and to reduce the area overhead of the Input Stage. With the elimination of the Input Stage and some restrictions on the arbitration scheme, we tan take away the one clock cycle delay and reduce the area overhead. Experimental results show that the end time of total bus transaction and the average latency time of improved Multi-Layer AHB BusMatrix are improved by $20\%\;and\;24\%$ respectively. in ease of executing a number of transactions by 4-beat incrementing burst type. Besides the total area and the clock period are reduced by $22\%\;and\;29\%$ respectively, compared with existing Multi-layer AHB BusMatrix.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.114.6-114
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• 2001

According to expansion of wireless communication system and mobile device, interest has been growing in personal navigation system integrated with wireless system. In portable consumer electronics, such as cellular phones, GPS and PDA, one of major design factors is the power consumption. Solutions of reducing the power dissipation are low voltage, low system clock power management and so on. This paper develops a GPS receiver based on the advanced power management algorithm that achieves very low average power consumption. Both RF and DSP chips are powered down and reactivated only when the position fixing is required. In order to run, the developed includes the RTC calibration function and the fast reacquisition function using XMC (eXtended Multiple Correlator) ...

• Journal of electromagnetic engineering and science
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• v.17 no.1
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• pp.39-43
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• 2017

In this paper, a systematic and statistical calibration technique was implemented to calibrate a high-speed signal converting system containing multiple digital-to-analog converters (DACs). The systematic error (especially the imbalance between DACs) in the current combining network of the multi-DAC system was modeled and corrected by calculating the path coefficients for individual DACs with wideband reference signals. Furthermore, by applying a Kalman filter to suppress noise from quantization and clock jitter, accurate coefficients with minimum noise were identified. For correcting an arbitrary waveform generator with two DACs, a co-simulation platform was implemented to estimate the system degradation and its corrected performance. Simulation results showed that after correction with 4.8 Gbps QAM signal, the signal-to-noise-ratio improved by approximately 4.5 dB and the error-vector-magnitude improved from 4.1% to 1.12% over 0.96 GHz bandwidth.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.37-43
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• 1999

Two-way addressing method has been proposed for efficient VLSI implementation of Euclidean calculation circuit for pipelined Reed-Solomon decoder. This new circuit is operating with single clock while exploiting maximum parallelism, and uses register addressing instead of register shifting to minimize the switching power. Logic synthesis shows the circuit with the new scheme takes 3,000 logic gates, which is about 40% reduction from the previous 5,000 gate implementation. Computer simulation also shows the power consumption is about 3mW. The previous implementation with multiple clock consumed about 5mW.

• Molecules and Cells
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• v.39 no.6
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• pp.484-494
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• 2016

Plant cells have a remarkable ability to induce pluripotent cell masses and regenerate whole plant organs under the appropriate culture conditions. Although the in vitro regeneration system is widely applied to manipulate agronomic traits, an understanding of the molecular mechanisms underlying callus formation is starting to emerge. Here, we performed genome-wide transcriptome profiling of wild-type leaves and leaf explant-derived calli for comparison and identified 10,405 differentially expressed genes (> two-fold change). In addition to the well-defined signaling pathways involved in callus formation, we uncovered additional biological processes that may contribute to robust cellular dedifferentiation. Particular emphasis is placed on molecular components involved in leaf development, circadian clock, stress and hormone signaling, carbohydrate metabolism, and chromatin organization. Genetic and pharmacological analyses further supported that homeostasis of clock activity and stress signaling is crucial for proper callus induction. In addition, gibberellic acid (GA) and brassinosteroid (BR) signaling also participates in intricate cellular reprogramming. Collectively, our findings indicate that multiple signaling pathways are intertwined to allow reversible transition of cellular differentiation and dedifferentiation.