• Title/Summary/Keyword: Multimedia Architecture

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Intelligent Architectural Design Module for Process Automation of Hanok Constructions (한옥 건축공정 자동화를 위한 지능형 설계모듈의 구현)

  • Ahn, Eun-Young
    • Journal of Korea Multimedia Society
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    • v.15 no.9
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    • pp.1156-1164
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    • 2012
  • Hanok is a cultural heritage containing our ancestor's life style intact and breathing alive with us until now. As Hanok has been concerned as a echo-friendly architecture, a new methodology for efficient construction without damaging the traditional construction process comes into request. The goal of this research is development of a architectural design tool based on the BIM(Building Information Modeling) for satisfying these demands. It will be usable to support whole process of the traditional building from digital design to production and construction. Firstly, we take a consideration of the traditional architecture reflecting the spirit of the age and suggest efficient design method for architectural components. Each components is pre-fabricated as a template representing similar components. All pre-fabricated components are designed by object-oriented concepts so, many variations for a component can be derived from the pre-fabricated component. Our method is helpful for reducing design errors because that it considers combining rule between connecting components in the template design. Moreover it is plugged in the commercial architectural CAD, so it can supports digital design not only traditional architecture but also fusion style mixed with modern architecture.

Color Media Instructions for Embedded Parallel Processors (임베디드 병렬 프로세서를 위한 칼라미디어 명령어 구현)

  • Kim, Cheol-Hong;Kim, Jong-Myon
    • Journal of KIISE:Computer Systems and Theory
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    • v.35 no.7
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    • pp.305-317
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    • 2008
  • As a mobile computing environment is rapidly changing, increasing user demand for multimedia-over-wireless capabilities on embedded processors places constraints on performance, power, and sire. In this regard, this paper proposes color media instructions (CMI) for single instruction, multiple data (SIMD) parallel processors to meet the computational requirements and cost goals. While existing multimedia extensions store and process 48-bit pixels in a 32-bit register, CMI, which considers that color components are perceptually less significant, supports parallel operations on two-packed compressed 16-bit YCbCr (6 bit Y and 5 bits Cb, Cr) data in a 32-bit datapath processor. This provides greater concurrency and efficiency for YCbCr data processing. Moreover, the ability to reduce data format size reduces system cost. The reduction in data bandwidth also simplifies system design. Experimental results on a representative SIMD parallel processor architecture show that CMI achieves an average speedup of 6.3x over the baseline SIMD parallel processor performance. This is in contrast to MMX (a representative Intel's multimedia extensions), which achieves an average speedup of only 3.7x over the same baseline SIMD architecture. CMI also outperforms MMX in both area efficiency (a 52% increase versus a 13% increase) and energy efficiency (a 50% increase versus an 11% increase). CMI improves the performance and efficiency with a mere 3% increase in the system area and a 5% increase in the system power, while MMX requires a 14% increase in the system area and a 16% increase in the system power.

Implementation of a 32-Bit RISC Core for Multimedia Portable Terminals (멀티미디어 휴대 단말기용 32 비트 RISC 코어 구현)

  • 정갑천;기용철;박성모
    • Proceedings of the IEEK Conference
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    • 2000.06b
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    • pp.226-229
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    • 2000
  • In this paper, we describe implementation of 32-Bit RISC Core for portable communication/information equipment, such as cellular telephones and personal digital assistants, notebook, etc. The RISC core implements the ARM$\^$R/V4 instruction set on the basis of low power techniques in architecture level and logic level. It operates with 5-stage pipeline, and has harvard architecture to increase execution speed. The processor is modeled and simulated in RTL level using VHDL. Behavioral Cache and MMU are added to the VHDL model for instruction level verification of the processor. The core is implemented using Mentor P'||'&'||'R tools with IDEC C-631 Cell library of 0.6$\mu\textrm{m}$ CMOS 1-poly 3-metal CMOS technology.

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Architecture and Call Setup Latency of a Softswitch for VoIP Service (소프트스위치 시스템의 호처리 성능 향상)

  • Kim, Sung-Chul;Yoo, Byun-Hoon;Lee, Byung-Ho
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.113-118
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    • 2005
  • Softswitch is the core BcN equipment which voice and multimedia switching based on the IP Technologies. It is designed to replace the Class 5(local Exchange) and Class 4(Toll Exchange) switch based on the circuit wired and wireless switching network technologies. Softswitch gets its name because typically it is a software based solution implemented on general purpose computers/servers. While the traditional PSTN switches are rely on dedicated facilities for T and S inter-connection and are designed primarily for voice communications. Packet based Softswitch is divided the control of call and bearer, very different from Public telephone network. Sometimes Call Agent or Media Gateway Controller, a key component in the VoIP solution, is also called Softswitch. This paper will suggest the software architecture of softswitch for performance in call processing part, also suggest the session management model to cover call setup latency.

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A study on the Development of General-Purpose Multimedia Processor Architecture (범용 멀티미디어 프로세서 구조 개발에 관한 연구)

  • 오명훈;박성모
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.1149-1152
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    • 1998
  • 멀티미디어 데이터를 아날로그 방식보다는 디지털 방식으로 처리하게 되면 여러 면에서 이득을 볼 수 있다. 멀티미디어 데이터를 디지털 방식으로 처리하는 방법 중 범용프로세서에서 멀티미디어 명령어에 의해 처리하게 되면 flexibility를 증가시키며 효율적으로 프로그램할 수 있다. 본 논문에서는 범용 프로세서 안에서 멀티미디어 데이터를 효율적으로 처리할 수 있는 명령어 집합 구조와 이를 수행할 수 있는 프로세서의 구조를 제안하고 이를 HDL(Hardware Description Language)로 동작레벨에서 기술하고 시뮬레이션 하였다. 제안된 멀티미디어 명령어는 특성에 따라 8개의 그룹에 총 55개의 명령어로 구성되며 64비트 데이터 안에서 각각 8비트의 8바이트, 16비트의 4하프워드, 32비트의 2워드의 부워드(subword) 데이터들을 병렬 처리한다. 모델링된 프로세서는 오픈아키텍쳐(Open Architecture)인 SPARC V.9 의 정수연산장치(Integer Unit)에 기반을 두었으며 하바드 구조를 지닌 5단 파이프라인 RISC 형태이다.

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Clustering Scheme for (m,k)-Firm Streams in Wireless Sensor Networks

  • Kim, Ki-Il
    • Journal of information and communication convergence engineering
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    • v.14 no.2
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    • pp.84-88
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    • 2016
  • As good example of potential application-specific requirement, (m,k)-firm real-time streams have been recently introduced to deliver multimedia data efficiently in wireless sensor networks. In addition to stream model, communication protocols to meet specific (m,k)-firm real-time streams have been newly developed or extended from existing protocols. However, since the existing schemes for an (m,k)-firm stream have been proposed under typical flat architecture, the scalability problem remains unsolved when the number of real-time flows increases in the networks. To solve this problem, in this paper, we propose a new clustering scheme for an (m,k)-firm stream. The two different clustering algorithms are performed according to either the (m,k)-firm requirement or the deadline. Simulation results are presented to demonstrate the suitability of the proposed scheme under hierarchical architecture by showing that its performance is acceptable irrespective of the increase in the number of flows.

Design and simulation of high performance computer architecture using holographic data storage system for database and multimedia workloads

  • Na, Jong-Whoa;Ryu, Dae-Hyun;Kim, Jung-Tae
    • Journal of information and communication convergence engineering
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    • v.1 no.4
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    • pp.169-173
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    • 2003
  • The performance of modern mainframe computers keeps increasing due to the advances in the semiconductor technology. However, the quest for the faster computer has never been satisfied. To overcome the discrepancy in the supply and demand, we studied a high performance computer architecture utilizing a three-dimensional Holographic Data Storage Systems (HDSS) as a secondary storage system. The HDSS can achieve a high storage density by utilizing the third dimension. Furthermore, the HDSS can exploit the parallelism by processing the two-dimensional data in a single step. To compare the performance of the HDSS with the conventional hard disk based storage system, we modeled the HDSS using the DiskSim simulation engine and performed the simulation study. Results showed that the HDSS can improve the access time by 1.7 times.

A Location Context Management Architecture of Mobile Objects for LBS Application

  • Ahn, Yoon-Ae
    • Journal of the Korean Data and Information Science Society
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    • v.18 no.4
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    • pp.1157-1170
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    • 2007
  • LBS must manage various context data and make the best use of this data for application service in ubiquitous environment. Conventional mobile object data management architecture did not consider process of context data. Therefore a new mobile data management framework is needed to process location context data. In this paper, we design a new context management framework for a location based application service. A suggestion framework is consisted of context collector, context manager, rule base, inference engine, and mobile object context database. It describes a form of rule base and a movement process of inference engine that are based on location based application scenario. It also presents an embodiment instance of interface which suggested framework is applied to location context interference of mobile object.

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A Memory-Efficient VLC Decoder Architecture for MPEG-2 Application

  • Lee, Seung-Joon;Suh, Ki-bum;Chong, Jong-wha
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.360-363
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    • 1999
  • Video data compression is a major key technology in the field of multimedia applications. Variable-length coding is the most popular data compression technique which has been used in many data compression standards, such as JPEG, MPEG and image data compression standards, etc. In this paper, we present memory efficient VLC decoder architecture for MPEG-2 application which can achieve small memory space and higher throughput. To reduce the memory size, we propose a new grouping, remainder generation method and merged lookup table (LUT) for variable length decoders (VLD's). In the MPEG-2, the discrete cosine transform (DCT) coefficient table zero and one are mapped onto one memory whose space requirement has been minimized by using efficient memory mapping strategy The proposed memory size is only 256 words in spite of mapping two DCT coefficient tables.

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Implementation of OPNET-based simulation model for the performance evaluation of ATM VP Transit network (ATM VP 중계망의 성능 시험을 위한 OPNET 기반의 시뮬레이션 모델 구현)

  • 구수용;김영탁
    • Journal of the Korea Society for Simulation
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    • v.8 no.4
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    • pp.125-136
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    • 1999
  • In the forthcoming public ATM/B-ISDN, the efficient resource management with pre-planned transit networking which public domain NNI signaling is essential to maintain high network utilization and to assure QoS to the multimedia service users. For this purpose the transit networks must be managed according to the bearer service capability which is defined by ATM Forum and ITU-T. In this paper, we introduce an implementation of ATM transit networking with ATM VP-XC(Virtual Path cross-connect) and US(Network Management System). The functions of ATM VP-XC and NMS have been simulated with OPNET 6.1 modules. We implemented the F4 OAM functions of ATM VP connection according to the ITU-T 1.610 recommendation. Also, the ATM VP transit networking is managed by the NMS according to the connection management architecture of the TWN(Telecommunications Management Network) /TINA ( Telecommunications Information Networking Architecture).

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