• Journal of Power Electronics
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• v.19 no.3
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• pp.727-743
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• 2019

This paper presents a pulse-width modulation strategy to eliminate the common mode voltage (CMV) with reduced CMV spikes in multilevel inverters since a high CMV magnitude and its fast variations dv/dt result in bearing failure of motors, overvoltage at motor terminals, and electromagnetic interference (EMI). The proposed method only utilizes the zero CMV states in a space vector diagram and it is implemented by a carrier-based pulse-width modulation (CBPWM) method. This method is generalized for odd number levels of inverters including neutral-point-clamped (NPC) and cascaded H-bridge inverters. Then it is extended to the over-modulation mode. The over-modulation mode is implemented by using the two-limit trajectory principle to maintain linear control and to avoid look-up tables. Even though the CMV is eliminated, CMV spikes that can cause EMI and bearing current problems still exist due to the deadtime effect. As a result, the deadtime effect is analyzed. By taking the deadtime effect into consideration, the proposed method is capable of reducing CMV spikes. Simulation and experimental results verify the effectiveness of the proposed strategy.

• Journal of Power Electronics
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• v.19 no.2
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• pp.413-430
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• 2019

This paper presents an optimum hybrid SVPWM technique for three-level voltage source inverters (VSIs). The proposed hybrid SVPWM technique aims to minimize total harmonic distortion (THD). A new parameter is introduced to incorporate the heterogeneous nature of switching sequences of SVPWM technique. The proposed hybrid SVPWM technique is implemented on a low-cost PIC microcontroller (PIC18F452) and verified experimentally with a 2 KVA three-phase three-level insulated gate bipolar transistor-based VSI. Optimum switching sequence results in the three-level inverter configuration are demonstrated. The proposed hybrid SVPWM technique improves the THD performance by 17.3% compared with the best available three-level SVPWM technique.

• Journal of Power Electronics
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• v.17 no.5
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• pp.1186-1194
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• 2017

This paper proposes an improved low frequency Selective Harmonic Mitigation-PWM (SHM-PWM) technique. The proposed method mitigates the low order harmonics of the output voltage up to the $50^{th}$ harmonic well and satisfies the grid codes EN 50160 and CIGRE-WG 36-05. Using a modified criterion for the switching angles, the range of the modulation index for non-linear SHM equations is improved, without increasing the switching frequency of the CHB converter. Due to the low switching frequency of the CHB converter, mitigating the harmonics of the converter up to the $50^{th}$ order and finding a wider modulation index range, the size and cost of the passive filters can be significantly reduced with the proposed technique. Therefore, the proposed technique is more efficient than the conventional SHM-PWM. To verify the effectiveness of the proposed method, a 7-level Cascaded H-bridge (CHB) converter is utilized for the study. Simulation and experimental results confirm the validity of the above claims.

• Journal of Power Electronics
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• v.14 no.2
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• pp.271-281
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• 2014

Fluctuating wind conditions necessitate the use of a variable speed wind turbine (VSWT) with a AC/DC/AC converter scheme in order to harvest the maximum power from the wind and to decouple the synchronous generator voltage and frequency from the grid voltage and frequency. In this paper, a combination of a three phase diode bridge rectifier (DBR) and a modified topology of the diode clamped multilevel inverter (DCMLI) has been considered as an AC/DC/AC converter. A control strategy has been proposed for the DCMLI to achieve the objective of grid interface of a wind power system together with local load compensation. A novel fixed frequency current control method is proposed for the DCMLI based on the level shifted multi carrier PWM for achieving the required control objectives with equal and uniform switching frequency operation for better control and thermal management with the modified DCMLI. The condition of the controller gain is derived to ensure the operation of the DCMLI at the fixed frequency of the carrier. The converter current injected into the distribution grid is controlled in accordance with the wind power availability. In addition, load compensation is performed as an added facility in order to free the source currents being fed from the grid of harmonic distortion, unbalance and a low power factor even though the load may be unbalanced, non-linear and of a poor power factor. The results are validated using PSCAD/EMTDC simulation studies.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.70-71
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• 2017

This paper presents a new cascaded boost multilevel converter topology for distributed generation (DG) systems. Most of DG systems, such as photovoltaic (PV), wind turbine and fuel cells, normally require the complex structure power converters, which makes the system expensive, complex and hard to control. However, the proposed converter topology can generate a much higher output voltage just by using the standard low-voltage switch devices and low voltage DC-sources in a simplified structure, also enhancing the reliability of the switch devices. Simulation and experimental results with a 1.2kW system are presented to validate the proposed topology and control method.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.635-639
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• 2004

This paper presents a simple PWM method to control three phase four leg multilevel inverters, which have been developed for supplying electrical power to three phase unbalanced load and for related power active filters. The method is derived from a general correlation between space vector PWM (SVPWM) method and carrier based PWM (CPWM) method. As an advantage, the simplicity and flexibility of the proposed CPWM control can be obtained and the complicated calculations of the 3-D SVPWM concepts can be avoided. The method has been mathematical formulated and demonstrated by simulation results.

• Journal of Electrical Engineering and Technology
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• v.13 no.2
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• pp.688-698
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• 2018

Quasi Z-Source Multilevel Inverter (QZMLI) topology has attracted grid connected Photovoltaic (PV) systems in recent days. So there is a remarkable research thrust in switching techniques and control strategies of QZMLI. This paper presents the mathematical analysis of Phase shift- Pulse Width Amplitude Modulation (PS-PWAM) for QZMLI and emphasizes on the advantages of the technique. The proposed technique uses the maximum and minimum envelopes of the reference waves for generation of pulses and proportion of it to generate shoot-through pulses. Hence, it results in maximum utilization of input voltage, lesser switching loss, reduced Total Harmonic Distortion (THD) of the output voltage, reduced inductor current ripple and capacitor voltage ripple. Due to these qualities, the QZMLI with PS-PWAM emerges to be the best suitable for PV based grid connected applications compared to Phase shift-Pulse Width Modulation (PS-PWM). The detailed math analysis of the proposed technique has been disclosed. Simulation has been performed for the proposed technique using MATLAB/Simulink. A prototype has been built to validate the results for which the pulses were generated using FPGA /SPARTAN 3E.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.385-387
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• 2008

Three-level Diode Clamped Multilevel Inverter, generally known as Neutral-Point-Clamped(NPC) inverter, has an inherent problem causing Neutral Point(NP) potential variation. Until now, in many literatures NP potential problem has been investigated and lots of solutions have also been proposed. However, in the case of NP potential variation was rarely published from the standpoint of reliability. In this paper, NP potential is analytically investigated both normal and fault conditions under carrier based PWM. Subsequently, relation between fault detection time and size of capacitor is analyzed. This information is explored by simulation results, which contribute to enhance the reliability of the NPC inverter system.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1167-1168
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• 2011

두 대의 동일한 H-bridge 모듈로 구성되는 Cascaded H-bridge 멀티레벨인버터는 출력전압에 5-레벨을 형성할 수 있으며 출력전압의 THD를 개선시키기 위해 PWM 스위칭을 적용할 수 있다. 출력필터 사이즈를 줄이기 위해 PWM 스위칭 주파수를 높일 수 있지만 스위칭 손실이 증가하게 된다. 본 논문에서는 이러한 경우 스위칭 손실을 저감시킬 수 있는 변형된 스위칭 패턴을 제안한다. Cascaded H-bridge 멀티레벨인버터의 특성을 고려하여 하단 H-bridge 모듈의 스위치는 기본 출력전압 레벨을 형성하도록 동작시키며, 상단 H-bridge 모듈 스위칭에 의한 출력값이 기본 전압레벨에 가감되어 PWM 출력전압 형성하도록 동작시킨다. 제안된 스위칭 패턴을 Cascaded H-bridge 멀티레벨인버터에 적용하여 기존 스위칭 방법과 비교 분석한다.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.369-373
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• 2001

Multilevel inverter has attracted great interest in high-voltage high-power field because of its less distorted output. In this paper, a direct torque control (DTC) technique based on a three-level neutral-point-clamped (NPC) inverter is presented. In order to solve the intrinsic neutral-point voltage-balancing problem and to obtain a high performance DTC, a special vector selection method is introduced and the concept of virtual vector is developed. By using the proposed PWM strategy, a MRAS speed sensor-less DTC drive can be achieved without sensing the neutral-point voltage, The strategy can be verified by simulation and experimental results.