• Proceedings of the KIPE Conference
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.225-227
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• 2008

This paper deals with the implementation on a Field Programmable Gate Array (FPGA) of PWM switching patterns for a voltage multilevel inverter. The reference data in main microcontroller is transmitted to the FPGA through 16 general purpose I/O ports. Herein, three-phase reference voltage signals are addressed by the last 2-bit (bit 15-14) and their data are assigned in remaining 14-bit, respectively. The carrier signals are created by 16-bit counter in up-down counting mode inside FPGA according to desirable topology. Each reference signal is compared with all carrier signals to generate corresponding PWM switching patterns for control of the multilevel inverter. Useful advantages of this scheme are easy implementation, simple software control and flexibility in adaptation to produce many PWM signals. Some simulations and experiments are carried out to validate the proposed method.

• Transactions of the Korean Society of Mechanical Engineers A
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• 제28권7호
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• pp.940-947
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• 2004

In this paper, an optimum design problem for endosseous implant in dentistry is studied to find best implant design. An optimum design problem is formulated to reduce stresses arising at the cortical as well as cancellous bones, in which sufficient design parameters are chosen for design definition that encompasses major implants in popular use. Optimization at once (OAO) with the large number of design variables, however, causes too costly solution or even failure to converge. A concept of multilevel optimization (MLO) is employed to this end, which is to group the design variables of similar nature, solve the sub-problem of smaller size for each group in sequence, and this is iterated until convergence. Each sub-problem is solved based on the response surface method (RSM) due to its efficiency for small sized problem.

• Journal of international Conference on Electrical Machines and Systems
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• 제3권3호
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• pp.305-311
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• 2014

In this paper, a new switching pattern is presented for multilevel inverters. With changing off-angel of each switch, the on time interval of all switches will approximately be equal and then the lifetime of inverter will increase, also using this method can reduce electrical stress on switches in higher levels of inverter. Switching angels as for desired modulation index are calculated using genetic algorithm whereas selective harmonics are controlled within the allowable range. The computed angels are simulated in Matlab/Simulink for respective circuits to validate the results.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅳ
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• pp.1747-1750
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• 2003

This paper proposes a multilevel vector error diffusion for fast and accurate color reproduction. Proposed method considered both hue angle and Euclidean distance during the multilevel vector error diffusion procedure to improve time complexity and output image quality In the error diffusion process, it can be determined whether error is diffused or not by comparing the vector norm and lightness value between original vector and error corrected vector of neighborhood pixels. For adaptive selection of output patch, this paper computes chroma value of error corrected vector and compares the hue angle between error corrected input vector and 64 primary color vectors.

• The Transactions of the Korean Institute of Electrical Engineers P
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• 제52권4호
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• pp.172-178
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• 2003

This paper examines the application of high voltage static var compensator(SVC) with cascade multilevel inverter which employs H-bridge inverter(HBI). This method has the primary advantage that the number of voltage levels can be increased for a given number of semiconductor devices when compared to the conventional control methods. The SVC system is modeled using the d-q transform which calculates the instantaneous reactive power. This model is used to design a controller and analyze the SVC system. From the mathematical model of the system, the design procedures of the circuit parameters L and C are presented in this thesis. To meet the specific total harmonic distortion(THD) and ripple factor of the capacitor voltage, the circuit parameters L and C are designed. Simulated and experimental results are also presented and discussed to validate the proposed schemes.

• Proceedings of the KIPE Conference
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• 전력전자학회 2018년도 전력전자학술대회
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• pp.105-107
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• 2018

This paper presents a new hybrid multilevel converter topology, which consists of a combination of the series connected switched capacitor units with boost ability, and an H-bridge with T-type bidirectional switches. The proposed converter boosts the input voltage without any bulky inductors, and has the small number of components, which can make the size and cost of a power converter greatly reduced. The output filter size and harmonics are also reduced by the high quality multilevel output. In addition, there is no need for complicated methods to balance the capacitor voltage. Simulation and experimental results with a nine-level converter system are presented to validate the proposed topology and modulation method.

• Proceedings of the KIPE Conference
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• 전력전자학회 2017년도 전력전자학술대회
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• pp.70-71
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• 2017

This paper presents a new cascaded boost multilevel converter topology for distributed generation (DG) systems. Most of DG systems, such as photovoltaic (PV), wind turbine and fuel cells, normally require the complex structure power converters, which makes the system expensive, complex and hard to control. However, the proposed converter topology can generate a much higher output voltage just by using the standard low-voltage switch devices and low voltage DC-sources in a simplified structure, also enhancing the reliability of the switch devices. Simulation and experimental results with a 1.2kW system are presented to validate the proposed topology and control method.

• Journal of Power Electronics
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• 제15권4호
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• pp.964-973
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• 2015

This paper presents a simple approach for the selective harmonic elimination (SHE) of multilevel inverter based on the transistor-clamped H-bridge (TCHB) family. The SHE modulation is derived from the sinusoidal voltage-angle equal criteria corresponding to the optimized switching angles. The switching angles are computed offline by solving transcendental non-linear equations characterizing the harmonic contents using the Newton-Raphson method to produce an optimum stepped output. Simulation and experimental tests are conducted for verification of the analytical solutions. An Altera DE2 field-programmable gate array (FPGA) board is used as the digital controller device in order to verify the proposed SHE modulation in real-time applications. An analysis of the voltage total harmonic distortion (THD) has been obtained for multiple output voltage cases. In terms of the THD, the results showed that the higher the number of output levels, the lower the THD due to an increase number of harmonic orders being eliminated.

• Proceedings of the KIPE Conference
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• 전력전자학회 2016년도 추계학술대회 논문집
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• pp.143-144
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• 2016

The circulating current control within the phase legs is one of the main control objectives in a modular multilevel converter (MMC) under different operating conditions. This paper proposes a control strategy of circulating currents in the MMC under unbalanced voltage by using a proportional-resonant (PR) controller. Under the unbalanced voltage, the circulating currents in the MMC consists of three components such as positive-sequence, negative-sequence, and zero-sequence circulating currents. With the PR controller, all components of the circulating current will be directly controlled in the stationary reference frame without decomposing into positive- and negative-sequence components. Thus, the ripples in the circulating currents and the DC current are suppressed under the unbalanced voltage. The effectiveness of the proposed method is verified by simulation results based on PSCAD/EMTDC simulation program.

• Journal of Industrial Technology
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• 제16권
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• pp.247-256
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• 1996

The multilevel grid file(MLGF) is a dynamic multidimensional file organization supporting multi-attribute accesses efficiently. The paper proposes new method for batch-constructing MLGFs. Our method consists of two phases. The first phase begins by relocating all the objects in order that logically adjacent objects in multidimensional domain space are clustered in one dimensional physical space. For this, our method employs the Z-ordering scheme, which effectively maps multidimensional space into one dimensional space preserving proximity. The second phase paginates the relocated objects and creates leaf level directory entries, each of which corresponds to a object page. Simultaneously, it performs same actions on the directory entries recursively in a bottom-up fashion until the root directory fits in a page. For performance evaluation, we analyze our method in terms of the number of page accesses. The result shows the optimality of our method.