• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.546-549
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• 1998

다치결정도 (multiple-valued decision diagram : MDD) 와 순서화된 다치결정도 (ordered MDD:OMDD)는 다치논리함수의 표현에 폭넓게 사용된다. p치 n변수인 경우 p/sup (n-1)/으로 증가하는 노드의 수는 ROMDD(reduced OMDD)를 사용하여 현저하게 감소시킬 수 있다. 그러나 다치와 다변수의 경우에는 더욱 많은 공정을 수반하게 된다. 이러한 단점을 보완하기 위해 honghai jiang이 제안한 2치시스템에서의 input implict/output explicit 관계를 갖는 OVAG(output value array graph)를 사용하여 다치논리함수를 표현한다. 그리고 MDD 표현이 어려운 상황에서 MOVAG(multi OVAG)를 사용하여 보다 쉽게 출력값을 배열하는 그래프를 이끌어 낼 수 있다. 본 논문에서는 MOVAG의 구성방법과 회로에서 MOVAG로으 변환에 대한 알고리듬을 제안하였고, 알고리듬에 의한 결과를 MDD와 비교하여 노드수 감소에 따르는 처리속도가 개선됨을 검증하였다.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 1999.05a
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• pp.75-79
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• 1999

다치결정도(Multiple-valued Decision Diagram : MDD)와 순서화된 다치결정도(Ordered MDD : OMDD)는 다치논리함수의 표현에 폭넓게 사용된다. p치 n변수 인 경우 p$^{(n-1)}$ 으로 증가하는 노드의 수는 ROMDD(Reduced OMDD)를 사용하여 현저하게 감소시킬 수 있다. 그러나 다치와 다변수의 경우에는 더욱 많은 공정을 수반하게 된다. 이러한 단점을 보완하기 위해 Honghai Jiang이 제안한 2치시스템에서의 input implict/output explicit 관계를 갖는 OVAG(Output Value Array Graph)를 사용하여 다치논리함수를 표현한다. 고리고 MDD 표현이 어려운 상황에서 MOVAG(Multi OVAG)를 사용하여 보다 쉽게 출력값을 배열하는 그래프를 이끌어 낼 수 있다. 본 논문에서는 MOVAG의 구성방법과 회로에서 MOVAG로의 변환에 대한 알고리즘을 제안하였고, 알고리즘에 의한 결과를 MDD와 비교하여 노드수 감소에 따르는 처리속도가 개선됨 을 검증하였다.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.449-449
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• 2000

Many researchers have studied architectures for non-Neumann's computers because of escaping its bottleneck. To avoid the bottleneck, a neuron-based computer has been developed. The computer has only neurons and their connections, which are constructed of the learning. But still it has information processing facilities, and at the same time, it is like as a simplified brain to make inference; it is called "neuron-computer". No instructions are considered in any neural network usually; however, to complete complex processing on restricted computing resources, the processing must be reduced to primitive actions. Therefore, we introduce the instructions to the neuron-computer, in which the most important function is implications. There is an implication represented by binary-operators, but general implications for multi-value or fuzzy logics can't be done. Therefore, we need to use Lukasiewicz' operator at least. We investigated a neuron-computer having instructions for general implications. If we use the computer, the effective inferences base on multi-value logic is executed rapidly in a small logical unit.

• Journal of the Korea Society of Computer and Information
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• v.17 no.6
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• pp.83-92
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• 2012

This paper suggests an improved method of grouping minterms based on the Decimal-Valued Matrix (DVM) method. The DVM is a novel approach to Boolean logic minimization method which was recently developed by this author. Using the minterm-based matrix layout, the method captures binary number based minterm differences in decimal number form. As a result, combinable minterms can be visually identified. Furthermore, they can be systematically processed in finding a minimized Boolean expression. Although this new matrix based approach is visual-based, the suggested method in symmetric grouping cell values can become rather messy in some cases. To alleviate this problem, the enhanced DVM method that is based on multi-level groupings of combinable minterms is presented in this paper. Overall, since the method described here provides a concise visualization of minterm groupings, it facilitates a user with more options to explore different combinable minterm groups for a given Boolean logic minimization problem.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.52-62
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• 2003

This paper discusses ternary logic gate, ternary D flip-flop, and ternary four-digit parallel input/output register. The ternary logic gates consist of n-channel pass transistors and neuron MOS(νMOS) threshold inverters on voltage mode. They are designed with a transmission function using threshold inverter that are in turn, designed using Down Literal Circuit(DLC) that has various threshold voltages. The νMOS pass transistor is very suitable gate to the multiple-valued logic(MVL) and has the input signal of the multi-level νMOS threshold inverter. The ternary D flip-flop uses the storage element of the ternary data. The ternary four-digit parallel input/output register consists of four ternary D flip-flops which can temporarily store four-digit ternary data. In this paper, these circuits use 3.3V low power supply voltage and 0.35m process parameter, and also represent HSPICE simulation result.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1195-1198
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• 1987

This paper develops algorithms of element generation, addition, multiplication and inversion based on GF($2^m$). Since these algorithms are implemented by general purpose computer, these are more efficient than the conventional algorithms(Table Lookup, Euclid's Algorithm) in each operation. It is also implied that they can be applied to not only the normally defined elements but the arbitrarily defined ones for constructing multi-valued logic function.

• Journal of IKEEE
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• v.18 no.4
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• pp.593-602
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• 2014

One of the purposes of an artificial neural netowrk(ANNet) is to implement the largest number of functions as possible with the smallest number of nodes and layers. This paper presents a CoreNet which has a multi-leveled input value and a multi-leveled output value with a 2-layered ANNet, which is the basic structure of an ANNet. I have suggested an equation for calculating the capacity of the CoreNet, which has a p-leveled input and a q-leveled output, as $a_{p,q}={\frac{1}{2}}p(p-1)q^2-{\frac{1}{2}}(p-2)(3p-1)q+(p-1)(p-2)$. I've applied this CoreNet into the simulation model 1(5)-1(6), which has 5 levels of an input and 6 levels of an output with no hidden layers. The simulation result of this model gives, the maximum 219 convergences for the number of implementable functions using the cot(${\sqrt{x}}$) input leveling method. I have also shown that, the 27 functions are implementable by the calculation of weight values(w, ${\theta}$) with the multi-threshold lines in the weight space, which are diverged in the simulation results. Therefore the 246 functions are implementable in the 1(5)-1(6) model, and this coincides with the value from the above eqution $a_{5,6}(=246)$. I also show the implementable function numbering method in the weight space.

• Journal of IKEEE
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• v.15 no.4
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• pp.354-362
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• 2011

One of the unsolved problems in Artificial Neural Networks is related to the capacity of a neural network. This paper presents a CoreNet which has a multi-leveled input and a multi-leveled output as a 2-layered artificial neural network. I have suggested an equation for calculating the capacity of the CoreNet, which has a p-leveled input and a q-leveled output, as $a_{p,q}=\frac{1}{2}p(p-1)q^2-\frac{1}{2}(p-2)(3p-1)q+(p-1)(p-2)$. With an odd value of p and an even value of q, (p-1)(p-2)(q-2)/2 needs to be subtracted further from the above equation. The simulation model 1(3)-1(6) has 3 levels of an input and 6 levels of an output with no hidden layer. The simulation result of this model gives, out of 216 possible functions, 80 convergences for the number of implementable function using the cot(x) input leveling method. I have also shown that, from the simulation result, the two diverged functions become implementable by precalculating the weight values. The simulation result and the precalculation of the weight values give the same result as the above equation in the total number of implementable functions.