• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8B
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• pp.787-795
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• 2002

This paper presents the architecture and the implementation of a 2K/4K/8K-point complex Fast Fourier Transform(FFT) processor for Orthogonal Frequency-Division Multiplexing (OFDM) system. The architecture is based on the Cooley-Tukey algorithm for decomposing the long DFT into short length multi-dimensional DFTs. The transposition memory, shuffle memory, and memory mergence method are used for the efficient manipulation of data for multi-dimensional transforms. Booth algorithm and the COordinate Rotation DIgital Computer(CORDIC) processor are employed for the twiddle factor multiplications in each dimension. Also, for the CORDIC processor, a new twiddle factor generation method is proposed to obviate the ROM required for storing the twiddle factors. The overall 2K/4K/8K-FFT processor requires 600,000 gates, and it is implemented in 1.8 V, 0.18 ${\mu}m$ CMOS. The processor can perform 8K-point FFT in every 273 ${\mu}s$, 2K-point every 68.26 ${\mu}s$ at 30MHz, and the SNR is over 48dB, which are enough performances for the OFDM in DVB-T.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.8
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• pp.722-730
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• 2014

Due to the advance of hardware, various devices have mobility features, and many applications need the data transmission. In addition, it is essential for latest smartphones to utilize multi-cores and multi-threads because of the enhancement of Application Processor. Therefore, this paper analyzes the performance/power consumption according to transmission rate, the number of cores, and that of threads in the system that is supposed to conduct data transmission and processing simultaneously. Through the analysis, this paper provides a direction for the proper number of threads in terms of performance improvement and efficient power consumption.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.1
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• pp.233-238
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• 2016

Recently, the multi-core processor architecture is widely adopted in the embedded processors for enhancing its performance. Multi-core processors are classified either as symmetric or asymmetric. Asymmetric multicore processors are known to score higher performance and more efficient than symmetric multi-core processors. In order to study the performance enhancement of asymmetric multi-core embedded processors over the symmetric ones, the trace-driven simulation has been executed for various asymmetric embedded dual-core, quad-core, octa-core and hexadeca-core processors and compared with the symmetric ones of similar hardware budget using MiBench benchmarks as input.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.1
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• pp.163-169
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• 2013

Recently, the importance of embedded system is growing rapidly. In-order to satisfy the real-time constraints of the system, high performance embedded processor is required. Therefore, as in general purpose computer systems, embedded processor should be designed as multicore architecture as well. Using MiBench benchmarks as input, the trace-driven simulation has been performed and analyzed for the 2-core to 16-core embedded processor architectures with different types of cores from simple RISC to in-order and out-of-order superscalar processors, extensively. As a result, the achievable performance is as high as 23 times over the single core embedded RISC processor.

• Journal of the Korea Computer Industry Society
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• v.5 no.2
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• pp.261-268
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• 2004

This study to design an optimum phase implementing a 256 phase Opto-ULSI processor for multi-function capable optical networks. The design of an 8 phase processor is already in construction and will provide the Initial base for experimentation and characterisation. The challenge is to be able to compensate for the non-linearity of the liquid crystal, find an optimum phase, and implement a larger scale Opto-ULSI processor. This research is oriented around the initial development of an 8 phase Opto-ULSI processor that implements a Beam Steering (BS) Opto-ULSI processor (OUP) for integrated intelligent photonic system (IIPS), while investigating the optimal phase characteristics and developing compensation for the non-linearity of liquid crystal.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.3
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• pp.158-164
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• 2008

This project investigates an optimum phase design implementing a 256 phase Opto-ULSI processor for multi-function capable optical networks. The design of an 8 phase processor is already in construction and will provide the initial base for experimentation and characterization. The challenge is to be able to compensate for the non-linearity of the liquid crystal, find an optimum phase, and implement a larger scale Opto-ULSI processor. This research is oriented around the initial development of an 8 phase Opto-ULSI processor that implements a Beam Steering(BS) Opto-ULSI processor(OUP) for integrated intelligent photonic system(IIPS), while investigating the optimal phase characteristics and developing compensation for the non-linearity of liquid crystal.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.3
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• pp.233-238
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• 2006

In order to solve power disturbances, power components measurement for both supply and demand side of power system must be implemented. This paper proposed a DSP (Digital Signal Processor)-based multi-channel (voltage 8-channel and current 10-channel) power components measurement system that simultaneously can measure and analyze power components for both supply md demand side. After voltage and current measurement accuracy revision using YOKOGAWA 2558, the developed system was tested in the field.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.9
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• pp.1444-1452
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• 1989

This paper describes the implementation of a real time fetal ECG monitoring system in which an adaptive multi-channel noise canceller is realized using the Texas Instruments TMS32020 progrmmmable ditital signal processor. An ECG signal from the electrode placed on the mother's abdomen and three ECGs from those on the chest are applied as the desired signal and the referened inputs, respectively, of the multi-channel filter. The coefficients of the filter are updated using the LMS algorithm such that the output of the multi-channel filter copies the maternal ECG embedded in the abdominal ECG. The enhanced fetal ECG is obtained by subtracting the filter output from the abdominal ECG, and the difference signal is recorded. Both off-line and on-line experimental results are presented to verify the effectiveness of the parameters for the digital signal processing algorithms and the prototype system.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.99-104
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• 2013

Recently smart devices which combine traditional electronic devices and personal computers, such as smart phones and smart TV, have caught people's eyes from all over the world. A multi-media SoC platform which embeds not only a calculating processor but also an operating system could provide an user-customized environment of several types of communication methods to PC or Internet. In this paper, we describe a multi-functioning SoC platform with video, audio and other communicating protocols based on Core-A processor and AMBA buses. To verify the designed multi-media SoC platform, JPEG decoding and ADPCM encoding/decoding algorithms are applied on it and the final decoding results are confirmed by video monitors and audio speakers.

• Journal of the Korea Computer Industry Society
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• v.3 no.1
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• pp.57-66
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• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast Fourier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi-valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like ［0,1,2,3］. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used as LUT(Look Up Table) Finally, for the compatibility with the binary system, multiple-valued hybrid-type FFT processor was proposed and designed using binary-four valued encoder, four-binary valued decoder, and the electric current mode CMOS circuit.