• Title/Summary/Keyword: Multi-processor

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Accelerating OpenVG and SVG Tiny with Multimedia Processors (멀티미디어 프로세서를 이용한 OpenVG 및 SVG Tiny의 가속)

  • Lee, Hwan-Yong;Baek, Nak-Hoon
    • Journal of the Korea Computer Graphics Society
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    • v.17 no.2
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    • pp.37-43
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    • 2011
  • OpenVG and SVG Tiny are the most widely used 2D vector graphics technologies for outputs in the various embedded environments including smart phones. Especially, to show high refresh rates on the high resolution screens, it is necessary to effectively accelerate them. Until now, OpenVG and SVG Tiny are available as hardware implementations such as the fully-dedicated graphics chips or full software implementations. Currently available vector graphics silicon chips are relatively expensive and require high power consumption. In contrast, previous full software implementations show lower performance even with almost 100% CPU usages, which would disrupt other multi-threaded applications, In this paper, we present a cost-effective way of accelerating both of OpenVG and SVG Tiny, based on the multimedia-processing hardware, which is wide-spread on the media devices and mobile phones. Through the effective use of these multimedia processors, we successfully accelerated OpenVG and SVG Tiny at least 3.5 times to at most 30 times, even with lower power consumption and lower CPU usage.

Development of the 'Three-stage' Bayesian procedure and a reliability data processing code (3단계 베이지안 처리절차 및 신뢰도 자료 처리 코드 개발)

  • 임태진
    • Korean Management Science Review
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    • v.11 no.2
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    • pp.1-27
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    • 1994
  • A reliability data processing MPRDP (Multi-Purpose Reliability Data Processor) has been developed in FORTRAN language since Jan. 1992 at KAERI (Korean Atomic Energy Research Institute). The purpose of the research is to construct a reliability database(plant-specific as well as generic) by processing various kinds of reliability data in most objective and systematic fashion. To account for generic estimates in various compendia as well as generic plants' operating experience, we developed a 'three-stage' Bayesian procedure[1] by logically combining the 'two-stage' procedure[2] and the idea for processing generic estimates[3]. The first stage manipulates generic plant data to determine a set of estimates for generic parameters,e.g. the mean and the error factor, which accordingly defines a generic failure rate distribution. Then the second stage combines these estimates with the other ones proposed by various generic compendia (we call these generic book type data). This stage adopts another Bayesian procedure to determine the final generic failure rate distribution which is to be used as a priori distribution in the third stage. Then the third stage updates the generic distribution by plant-specific data resulting in a posterior failure rate distribution. Both running failure and demand failure data can be handled in this code. In accordance with the growing needs for a consistent and well-structured reliability database, we constructed a generic reliability database by the MPRDP code[4]. About 30 generic data sources were reviewed and available data were collected and screened from them. We processed reliability data for about 100 safety related components frequently modeled in PSA. The underlying distribution for the failure rate was assumed to be lognormal or gamma, according to the PSA convention. The dependencies among the generic sources were not considered at this time. This problem will be approached in further study.

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Design of an Efficient Parallel High-Dimensional Index Structure (효율적인 병렬 고차원 색인구조 설계)

  • Park, Chun-Seo;Song, Seok-Il;Sin, Jae-Ryong;Yu, Jae-Su
    • Journal of KIISE:Databases
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    • v.29 no.1
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    • pp.58-71
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    • 2002
  • Generally, multi-dimensional data such as image and spatial data require large amount of storage space. There is a limit to store and manage those large amount of data in single workstation. If we manage the data on parallel computing environment which is being actively researched these days, we can get highly improved performance. In this paper, we propose a parallel high-dimensional index structure that exploits the parallelism of the parallel computing environment. The proposed index structure is nP(processor)-n$\times$mD(disk) architecture which is the hybrid type of nP-nD and lP-nD. Its node structure increases fan-out and reduces the height of a index tree. Also, A range search algorithm that maximizes I/O parallelism is devised, and it is applied to K-nearest neighbor queries. Through various experiments, it is shown that the proposed method outperforms other parallel index structures.

The Design and Performance Verification of Real-Time Inspection Equipment Software based on Windows Operating System (윈도우 운영체제 기반의 실시간 점검장비 소프트웨어 설계 및 성능검증)

  • Kim, Hyo-Joung;Heo, Yong-Kwan;Kwon, Byung-Gi
    • The Journal of the Korea Contents Association
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    • v.17 no.10
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    • pp.1-8
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    • 2017
  • As the recent advancement of military equipment has been accelerated, it is becoming more important to act as an inspection device that verifies the performance of equipment in real time. Most of the inspection equipments were developed on the Windows OS based system. considering development convenience and development period. However, sice the data communication between these models occurs asynchronously, there is a problem that it is difficult to guarantee real-time performance of the window-based inspection equiment. To solve these problems, we use real-time commercial solutions to guarantee the real-time performance of Windows-based inspection equipment. In this paper, we propose a method of designing and implementing the inspection equipment software based on Real-Time implanted Kernel-Multi Processor (RTiK-MP) operating in Windows environment. In addition, real-time performance data accuracy was measured through a high-speed communication tool and interlocking test to verify the performance of the inspection device based on the real-time porting kernel.

Real-Time Kernel for Linux based on ARM Processor, RTiKA (Real-Time Implant Kernel For ARMLinux) (ARM 프로세서 기반의 리눅스를 위한 실시간 확장 커널 (RTiKA, Real-Time implant Kernel for ARMLinux))

  • Lee, Seung-Yul;Lee, Sang-Gil;Lee, Cheol-Hoon
    • The Journal of the Korea Contents Association
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    • v.17 no.10
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    • pp.587-597
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    • 2017
  • Recently, the demand for real-time performance in mobile environment is increasing due to the improvement of hardware performance, however a GPOS(General-Purpose Operating System) such as Android and Linux do not provide real-time performance. We developed RTiK(Real-Time implant Kernel) for this problem, but it has the disadvantage of supporting only x86 Architecture. In this paper, we designed and implemented a RTiKA(Real-Time implanted Kernel for ARM) to support real-time in ARM Linux. We used MCT(Multi-Core Timer) timer which replaces Local APIC Timer for real-time support, and we measured the period of generated real-time task for performance verification and evaluation. As the recent the RTiKA can guarantee the operating of several real-time tasks based on the cycle of 1ms.

Integrated Middleware for Real-Time Device Drivers on Windows (윈도우즈 상에서 실시간 디바이스 드라이버를 위한 통합 미들웨어)

  • Jo, Ah-Ra;Song, Chang-In;Lee, Cheol-Hoon
    • The Journal of the Korea Contents Association
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    • v.13 no.3
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    • pp.22-31
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    • 2013
  • For the case of test equipments requiring data accuracy, real-time is highly required in acceptance test for performance evaluation of developed weapons. For convenience' sake, test equipments are usually developed using Windows. However Windows does not support real-time in itself. Thus, in this paper, so as to reduce development time and expenses, we design and implement an integrated middleware for real-time device drivers using RTiK-MP. Using DLL, we also support user API's for the sake of development convenience without details of the complex RTiK-MP structure. We evaluate the performance of the proposed integrated middleware using the RDTSC command which returns the number of CPU clock ticks. The evaluation results show that it operates correctly within error ranges in the periods of 1ms and 4ms for the cases of TCP/IP and RS-232, respectively.

The Design of MPI Hardware Unit for Enhanced Broadcast Communication (효율적인 브로드캐스트 통신을 지원하는 MPI 하드웨어 유닛 설계)

  • Yun, Hee-Jun;Chung, Won-Young;Lee, Yong-Surk
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.11B
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    • pp.1329-1338
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    • 2011
  • This paper proposes an algorithm and hardware architecture for a broadcast communication which has the worst bottleneck among multiprocessor using distributed memory architectures. In conventional systems, collective communication is converted into point-to-point communications by MPI library cell without considering the state of communication port of each processing node which represents the processing node is in busy state or free state. If conflicting point-to-point communication occurs during broadcast communication, the transmitting speed for broadcast communication is decreased. Thus, this paper proposed an algorithm which determines the order of point-to-point communications for broadcast communication according to the state of each processing node. According to the state of each processing node, the proposed algorithm decreases total broadcast communication time by transmitting message preferentially to the processing node with communication port in free state. The proposed MPI unit for broadcast communication is evaluated by modeling it with systemC. In addition, it achieved a highly improved performance for broadcast communication up to 78% with 16 nodes. This result shows the proposed algorithm is useful to improving total performance of MPSoC.

SoC Design of Speaker Connection System by Efficient Cosimulation (효율적인 통합시뮬레이션에 의한 스피커 연결 시스템의 SoC 설계)

  • Song, Moon-Vin;Song, The-Hoon;Oh, Chae-Gon;Chung, Yun-Mo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.10 s.352
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    • pp.68-73
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    • 2006
  • This, paper proposes a cosimulation methodology that results in an efficient SoC design as well as fast verification by integrating HDL, SystemC, and algorithm-level abstraction using the design tools Active-HDL and Matlab's Simulink. To demonstrate the proposed design methodology, we implemented the design technique on a serial connection multi-channel speaker system. We have demonstrated the proposed cosimulation method utilizing an ARM processor based SoC Master board with the AMBA bus interface and a Xilinx Vertex4 FPGA. The proposed method has the advantage of simultaneous simulation verification of both software and hardware parts in high levels of abstraction mixed with some performance critical parts in more concrete RTL codes. This allows relatively fast and easy design of a speaker connection system which typically requires significant amount of data processing for verification.

3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

  • Lee, Kang-Wook
    • Journal of the Microelectronics and Packaging Society
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    • v.22 no.2
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    • pp.11-19
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    • 2015
  • Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

Design of Cic roll-off Compensation Filter in Digital Receiver For W-CDMA NODE-B (W-CDMA 기지국용 디지털 수신기의 CIC 롤 오프 보상필터 설계)

  • 김성도;최승원
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.40 no.12
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    • pp.155-160
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    • 2003
  • Owing to the advances in ADC and DSP technologies, signals in If band, which once had to be processed in analog technology, can new be digitally processed. This is referred to as "Digital IF" or "Digital Radio", which is a preliminary stage of SDR. Applying the digital radio technology to a multi-carrier receiver design, a processing gain is generated through an over-sampling of input data. In the digital receiver, decimation is performed for reducing the computational complexity CIC and half band filter is used together with the decimation as an anti-alising filter. The CIC filter, however, should introduce the roll-off phenomenon in the passband, which causes the receiving performance to be considerably degraded due to the distorted Passband flatness of receiving filter. In this paper, we designed a CIC roll-off compensation filter for W-CDMA digital receiver. The performance of the proposed compensation filter is confirmed through computer simulations in such a way that the BER is minimized by compensating the roll-off characteristics.off characteristics.