• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.113.3-113
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• 2001

In this paper, we have designed the VHDL module of DS/SS QPSK wireless modem processor for digital data communication. The spread spectrum method is used for modern processor, because this method guarantees good frequency efficiency and higher security. Also, it guarantees good performance in digital communication system under multi-path interferences. The differential encoder and decoder are used for simple circuit composition in the signal detection. For the synchronization of receiver, matched filter and power detector are used. And the IF modulation/demodulation of QPSK method is used in the digital level. The transmitter of VHDL modem processor consists of differential encoder, PN code generator, and QPSK ...

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1990년도 한국자동제어학술회의논문집(국제학술편); KOEX, Seoul; 26-27 Oct. 1990
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• pp.923-928
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• 1990

This paper describes the design and implementation of a real-time, high-precision vision system and its application to SMT(surface mounting technology) automation. The vision system employs a 32 bit MC68030 as a main processor, and consists of image acquisition unit. DSP56001 DSP based vision processor, and several algorithmically dedicated hardware modules. The image acquisition unit provides 512*480*8 bit image for high-precision vision tasks. The DSP vision processor and hardware modules, such as histogram extractor and feature extractor, are designed for a real-time excution of vision algorithms. Especially, the implementation of multi-processing architecture based on DSP vision processors allows us to employ more sophisticated and flexible vision algorithms for real-time operation. The developed vision system is combined with an Adept Robot system to form a complete SMD system. It has been found that the vision guided SMD assembly system is able to provide a satisfactory performance for SND automation.

• 대한전자공학회논문지
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• 제24권6호
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• pp.1040-1048
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• 1987

We propose a hardware architecture called Multiring which is applicable for various geometrical operations on rectilinear objects such as design rule checking in VLSI layout and many image processing operations including noise suppression and coutour extraction. It has both a fast execution speed and extremely high flexibility. The whole architecture is mainly divided into four parts` I/O between host and Multiring, ring memory, linear processor array and instruction decoder. Data transmission between host and Multiring is bit serial thereby reducing the bandwidth requirement for teh channel and the number of external pins, while each row data in the bit map stored in ring memory is processed in the corresponding processor in full parallelism. Each processor is simultaneously configured by the instruction decoder/controller to perform one of the 16 basic instructions such as Boolean (AND, OR, NOT, and Copy), geometrical(Expand and Shrink), and I/O operations each ring cycle, which gives Multiring maximal flexibility in terms of design rule change or the instruction set enhancement. Correct functional behavior of Multiring was confirmed by successfully running a software simulator having one-to-one structural correspondence to the Multiring hardware.

• 대한전자공학회논문지
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• 제27권6호
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• pp.963-971
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• 1990

This paper proposes a memory intensive VLSI architecture for the realization of real-time 3x3 neighborhood processor based on the distributed arithmetic. The proposed architecture is characterized by a bit serial and multi-kernel parallel processing which exploits the pixel kernel parallelism and concurrency. The chip implements 8 neighborhood processing elements in parallel with efficirnt input and output modules which operate concurrently. Besides the a4chitectural design of a neighborhood processor, the design methodology using module generator concept has been considered and MOGOT(MOdule Generator Oriented VLSI design Tool) has been constructed based on the workstation. Based on these design environments MOGOT, it has been shown that the main part of the suggested architecture can be designed efficiently using 2\ulcorner double metal CMOS technology. It includes design of input delay and data conversion module, look-up table for inner product operation, carry save accumulator, output data converter and delay module, and control module.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권4호
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• pp.194-198
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• 2003

A 16-bit adiabatic low-power Micro-processor core is designed. The processor consists of control block, multi-port register file and ALU. A simplified four-phase clock generator is designed to provide supply clocks for adiabatic processor. All the clock line charge on the capacitive interconnections is recovered to recycle the energy. Adiabatic circuits are designed based on ECRL(efficient charge recovery logic) and $0.35\mu\textrm$ CMOS technology is used. Simulation results show that the power consumption of the adiabatic Microprocessor core is reduced by a factor of 2.9~3.1 compared to that of conventional CMOS Microprocessor

• 소성∙가공
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• 제12권6호
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• pp.542-549
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• 2003

Three-dimensional forging analysis becomes an inevitable tool to make design process more reliable and more producible. In this study, in order to make the investigation for three-dimensional forging analysis more conveniently and accurately, a new post processor was developed. For post-processing of multi-stage forging simulation, efficient data structure was proposed and applied by using STL. New file architecture was developed to handle successive and huge data efficiently, common in three-dimensional forging analysis. Since sectioning and flow tracing plays an important role in the investigation of analysis result, we developed an algorithm suitable for 4-node and 10-node tetrahedron. This flow tracing algorithm can trace and reverse-trace flow through remeshing. Developed program shows good performance and functionality. Especially, a big size problem can be handled easily due to proposed data structure and file architecture.

• 한국우주과학회:학술대회논문집(한국우주과학회보)
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• 한국우주과학회 2004년도 한국우주과학회보 제13권2호
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• pp.364-367
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• 2004

This paper presents the flight software of KoDSat (KSLV-l Demonstration Satellite) which performs demonstrating the KSLV-l (Korea Space Launch Vehicle-l)'s satellite launch capability. The KoDSat Flight Software executes in a single-processor, multi-function flight computer on the spacecraft, the OBC (On Board Computer). The flight software running on the single processor is responsible for all real-time processing associated with: processor startup and hardware initialization, task scheduling, RS422 handling function, command and data handling including uplink command and down-link telemetry, attitude determination and control, battery state of charge monitoring and control, thermal control processing.

• 대한설비공학회:학술대회논문집
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• 대한설비공학회 2008년도 동계학술발표대회 논문집
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• pp.475-480
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• 2008

A pre/post processor program based GUI(Graphic User Interface) by using the MFC and OpenGL library in the Windows OS have been developed for the analysis of the passenger flow. Using this program, users are able to generate and modify the meshes of multi-storied subway station, set all the parameters for the solver, and obtain the results of the simulation such as transient passenger motions and passenger streak lines in 3-dimensional graphic view.

• 한국통신학회논문지
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• 제13권1호
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• pp.28-40
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• 1988

근래에 들어 통신기기의 지능화에 대한 필요성과 프로세서 가격의 저렴화가 서로 부합되어 하나의 시스템내에 다수의 프로세서를 실장하는 것이 공통된 경향이다. 본 논문에서는 이와 같이 다수의 근접된 프로세서 상호간에 적용 가능한 통신 방식으로 "근접된 프로세서간 통신 방식에 관한 연구"에서 이미 제안한 "통신예약 버스" 방식에 적용할 수 있는 하드웨어 및 소프트웨어를 개발, 제시하였으며 이에대한 실험을 통하여 본 방식의 타당성 및 관련 하드웨어와 소프트웨어의 실용성을 검증하였다.와 소프트웨어의 실용성을 검증하였다.

• 대한전기학회논문지:시스템및제어부문D
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• 제52권5호
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• pp.295-304
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• 2003

In this paper, we proposed a hardware-oriented Genetic Algorithm Processor(GAP) based on subpopulation architecture for high-performance convergence and reducing computation time. The proposed architecture was applied to enhancing population diversity for correspondence to premature convergence. In addition, the crossover operator selection and linear ranking subpop selection were newly employed for efficient exploration. As stochastic search space selection through linear ranking and suitable genetic operator selection with respect to the convergence state of each subpopulation was used, the elapsed time of searching optimal solution was shortened. In the experiments, the computation speed was increased by over $10\%$ compared to survival-based GA and Modified-tournament GA. Especially, increased by over $20\%$ in the multi-modal function. The proposed Subpop GA processor was implemented on FPGA device APEX EP20K600EBC652-3 of AGENT 2000 design kit.