• Title/Summary/Keyword: Multi-level switching

Search Result 177, Processing Time 0.035 seconds

A Hybrid Active Power Filter for Electric-Railway Systems using Multi-Level Inverters (멀티레벨 인버터를 이용한 전기철도용 하이브리드 능동전력필터)

  • Kim Yoon-Ho;Kim Soo-Hong;Rho Sung-Chan;Lee Kang-Hee
    • Proceedings of the KSR Conference
    • /
    • 2004.06a
    • /
    • pp.1334-1339
    • /
    • 2004
  • This paper proposes transformerless power conversion system consisting of a single-phase diode rectifier and a shunt hybrid filter for the electric-railway system. The hybrid filter consists of a single tuned LC filter per a phase and a low-rated NPC type multi-level inverter. Compared with conventional active filters. Transformers are not used. Also, LC filter works as not only a harmonic filter tuned at the 5th harmonic frequency but also a switching-ripple filter. The rating of the active filter can be decreased by using a NPC type multi-level inverter. The simulation results confirm the validity of the system.

  • PDF

A Hybrid Active Power Filter for Electric-Railway Systems using Multi-Level Inverters (멀티레벨 인버터를 이용한 전기철도용 하이브리드 능동전력필터)

  • Kim Yoon-Ho;Kim Soo-Hong;Rho Sung-Chan;Lee Kang-Hee
    • Proceedings of the KSR Conference
    • /
    • 2004.06a
    • /
    • pp.1427-1432
    • /
    • 2004
  • This paper proposes transformerless power conversion system consisting of a single-phase diode rectifier and a shunt hybrid filter for the electric-railway system. The hybrid filter consists of a single tuned LC filter per a phase and a low-rated NPC type multi-level inverter. Compared with conventional active filters. Transformers are not used. Also, LC filter works as not only a harmonic filter tuned at the 5th harmonic frequency but also a switching-ripple filter. The rating of the active filter can be decreased by using a NPC type multi-level inverter. The simulation results confirm the validity of the system

  • PDF

Design of EMI filters for an Induction Motor Drive System with Multi-level inverters (멀티레벨 인버터를 이용한 3상 유도전동기 구동 시스템의 EMI 필터 설계)

  • Kim, Soo-Hong;Ahn, Young-Oh;Bang, Sang-Seok;Kim, Kwang-Seob;Kim, Yoon-Ho
    • The Transactions of the Korean Institute of Electrical Engineers B
    • /
    • v.55 no.5
    • /
    • pp.265-270
    • /
    • 2006
  • In this paper EMI problems with induction motor drive system using multi-level inverters are investigated. The high power multi-level inverter usually operates with low switching frequency and produces large noises. Generally, EMI consists of the conduction component through source lines and emission component emitted to the space. This conduction component can be classified to the common-mode between source line and ground, and the normal-mode between lines. The EMI filters for the induction motor drive system are designed and implemented to reduce EMI noise. Finally the designed system is verified by the experiment. The experimental results show that both the normal mode and common mode noises are greatly reduced compared to the system without filters.

The Current Control with Multi-level Converter on Transformer type (변압기 방식 멀티레벨 컨버터의 전류제어)

  • Kim C. S.;Kwak D. G.;Chun J. H.;Suh K. Y.;Lee H. W.
    • Proceedings of the KIPE Conference
    • /
    • 2001.07a
    • /
    • pp.215-218
    • /
    • 2001
  • This paper is proposed a sinusoidal input current multi-level ac-dc converter using transformer. The multi-level converter which controls input current by combining Buck converter to Improve input current characteristics. This method, which is multiplying and duplicating output of converter of equal capacity, is able to control unit power factor of input current, reduce the problem caused by high frequency switching, and apply to high power converter because filter is not necessary The feasibility of the circuit is verified by computer simulation using PSIM

  • PDF

Switching signal of Cascaded HBML inverter employing the identical Transformer (동일한 변압기 용량을 갖는 직렬형 HBML 인버터의 스위칭 신호)

  • Lee, S.H.;Park, S.J.;Moon, C.J.;Ahn, J.W.;Gwon, S.J.;Lee, M.H.
    • Proceedings of the KIPE Conference
    • /
    • 2005.07a
    • /
    • pp.651-654
    • /
    • 2005
  • In this paper, an efficient switching pattern to equalize the size of transformer is proposed for a multi-level inverter employing cascaded transformers. It is based on the prior selected harmonic elimination PWM(SHEPWM) method. Because the maximum magnetic flux imposed on each transformer becomes exactly equal each to each, all transformers can be designed with the same size regardless of their position. Therefore, identical full-bridge inverter units can be utilized, thus improving modularity and manufacturability. The fundamental idea of the proposed switching pattern is illustrated and the analyzed theoretically. The validity of the proposed switching strategy is verified by experimental results.

  • PDF

A Study on The Multi-PWM Inverter by Complementary Transistor (상보형(相補形) 트랜지스터에 의한 다중(多重) PWM 인버터에 관한 연구)

  • Chung, Yon-Tack;Lee, Jong-Soo;Bee, Sang-Jun;Back, Jong-Hyun
    • Proceedings of the KIEE Conference
    • /
    • 1989.07a
    • /
    • pp.515-517
    • /
    • 1989
  • This PWM inverter are used bridge circuit of two pair complementary transistor at each phase. The operation signals are 3 level PWM wave of W type and M type modulation, Which were obtained from switching time data by switching position calculation of triangular and sine wave. The output voltage waveforms of this inverter have the 5 level phase voltage and the 9 level line voltage of PWM.

  • PDF

A Multi-Stair Case Wave PWM Inverter by Complementary Transistor (상보형 트랜지스테에 희한 다단 계단파 PWN 인버터)

  • 정연택;이종수;이달해;배상준;백종현;배영호
    • The Transactions of the Korean Institute of Electrical Engineers
    • /
    • v.39 no.2
    • /
    • pp.157-163
    • /
    • 1990
  • The PWM inverter investigated in this paper utilizes a bridge type current sharing reactor circuit with tow pairs of complementary transistor at each phase. The driving signals for this inverter are 3 level PWM waves of W type an M type modulation, which are obtained from a microprocessor based on the switching time data obtained by switching position calculation of triangular and sine modulation wave. The output voltage waveforms of this inverter have 5 level phase voltage and 9 level line voltage of PWM. The harmonics of the output voltage are reduced to half when it is compared with single CTI, and the occurrence of harmonics is also reduced.

  • PDF

High Speed Serial Link Transmitter Using 4-PAM Signaling (4-PAM signaling을 이용한 high speed serial link transmitter)

  • Jeong, Ji-Kyung;Lee, Jeong-Jun;Burm, Jin-Wook;Jeong, Young-Han
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.46 no.11
    • /
    • pp.84-91
    • /
    • 2009
  • A high speed serial link transmitter using multi-level signaling is proposed. To achieve high data rate m high speed serial link, 4-pulse amplitude modulation (PAM) is used. By transmitting 2 bit data in each symbol time, high speed data transmission, two times than binary signaling, is achieved. The transmitter transmits current-mode output instead of voltage-mode output Current-mode output is much faster than voltage-mode output, so higher data transmission is available by increasing switching speed of driver. $2^5-1$ pseudo-random bit sequence (PRBS) generator is contained to perform built-in self test (BIST). The 4-PAM transmitter is designed in Dongbu HiTek $0.18{\mu}m$ CMOS technology and achieves 8 Gb/s, 160 mV of eye height with 1.8 V supply voltage. The transmitter consumes only 98 mW for 8 Gb/s transmission.

Hazard-Free Multi-valued sequential logic cirwits (Hazard-Free를 考慮한 多値順序論理回路)

  • 林寅七 = In-Chil Lim;李秀英
    • Communications of the Korean Institute of Information Scientists and Engineers
    • /
    • v.5 no.2
    • /
    • pp.94-98
    • /
    • 1987
  • Multi-Valued(MV) sequential logic circuits are proposed which are free from HAZARD. In this paper, HAZARD is classified Function and Logic HAZARD, and MV switching function in which they are eliminated is described. Also, the basic MV memory elements which can be realized without HAZARD are presented, so that suggest the realizability in the large-scale MV logic system based on these elements.

Selective Harmonic Elimination in Multi-level Inverters with Series-Connected Transformers with Equal Power Ratings

  • Moussa, Mona Fouad;Dessouky, Yasser Gaber
    • Journal of Power Electronics
    • /
    • v.16 no.2
    • /
    • pp.464-472
    • /
    • 2016
  • This study applies the selective harmonic elimination (SHE) technique to design and operate a regulated AC/DC/AC power supply suitable for maritime military applications and underground trains. The input is a single 50/60 Hz AC voltage, and the output is a 400 Hz regulated voltage. The switching angles for a multi-level inverter and transformer turns ratio are determined to operate with special connected transformers with equal power ratings and produce an almost sinusoidal current. As a result of its capability of directly controlling harmonics, the SHE technique is applicable to apparatus with congenital immunity to specific harmonics, such as series-connected transformers, which are specially designed to equally share the total load power. In the present work, a single-phase 50/60 Hz input source is rectified via a semi-controlled bridge rectifier to control DC voltage levels and thereby regulate the output load voltage at a constant level. The DC-rectified voltage then supplies six single-phase quazi-square H-bridge inverters, each of which supplies the primary of a single-phase transformer. The secondaries of the six transformers are connected in series. Through off-line calculation, the switching angles of the six inverters and the turns ratios of the six transformers are designed to ensure equal power distribution for the transformers. The SHE technique is also employed to eliminate the higher-order harmonics of the output voltage. A digital implementation is carried out to determine the switching angles. Theoretical results are demonstrated, and a scaled-down experimental 600 VA prototype is built to verify the validity of the proposed system.