• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2007년도 추계학술대회 논문집
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• pp.107-109
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• 2007

LED is expected as an environmentally friendly light source with its good reliability and long lifetime. A few ten mW white LED can substitute for the indicator light source, and it is required to study several watt multi-chip semiconductor light sources in order to replace the light sources for general illumination such as incandescent lights and fluorescent lamps. Since the optical technology used for several mW white LED light source uses only 30% to 50% of the light, it is required to develop the design technology of optical system and lens to improve the efficiency more than 80% for insuring the high power of white LED. In this paper, we designed and fabricated new structure reflector to increase the efficiency.

• 전자공학회논문지A
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• 제31A권10호
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• pp.141-151
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• 1994

this paper describes the design and implementation of a RISC processor for embedded control systems. This RISC processor integrates a register file, a pipelined execution unit, a FPU interface, a memory interface, and an instruction prefetcher. Its characteristics include both single cycle executions of most instructions in a 2 phase 20 MHz frequency and the worst case interrupt latency of 7 cycles with the vectored interrupt handling that makes it possible to be applicable to the real time processing system. For efficient handling of multi-cycle instructions, data stationary hardwired control scheme equippedwith cycle counter was used. This chip integrates about 139K transistors and occupies 9.1mm$\times$9.1mm in a 1.0um DLM CMOS technology. The power dissipation is 0.8 Watts from a 5V supply at 20 MHz operation.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2002년도 ICCAS
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• pp.121.1-121
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• 2002

Calculation unit and peripheral units that are used to make the position controller are embedded to one chip FPGA. $\textbullet$ Feed-forward PID controller and interpolator in the calculation unit mitigate frequent context switching. $\textbullet$ The peripheral units reduce the size of the joints position control board. $\textbullet$ Because the calculation unit is designed with pipeline structure, it has the advantages to apply to the multi joints.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.256-259
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• 2003

In this paper, a design of multi-layered BPF(bandpass filter) using LTCC(Low Temperature Co-fired Ceramic) process by a lumped-elements is proposed for SOP(system-on-a-chip) of wireless communication systems. The proposed BPF improved a characteristic of rejection band to build an attenuation pole caused by structurally adjacent co-inductance and coupling. The simulation data shows a bandwidth of 90MHz from a center frequency of 2.4GHz, a return loss of 27dB, an insertion loss of 3.2dB, and an attenuation of at least 20dBc at $f_0{\pm}250MHz$. Simulations have used serenade circuit simulation and HFSS EM simulation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 하계학술대회 논문집 A
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• pp.334-336
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• 1994

The conventional APF(Active Power Filter) system performs only function which is compensated for source harmonic by injecting harmonic compensation current as well as reactive power component by PWM. This paper presents a new APF which provides the combined functions of VC(Voltage Compensator) and conventional APF, because the structure of APF is similar to stand- alone UPS in parallel type. Single-chip microprocessor plays an important role in controlling each function. Simulation obtained from ACSL are shown to verify multi-functions of new APP.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1952-1955
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• 2002

Multiple access interference (MAI) and multi path interference(MPI) degrades the system performance in the DS-CDMA(direct-sequence code-division multiple- access)systems .0 this paper, a generalized construction method fer 2$\^$n/(n=1,2,3) phase preferred pairs(PP) with zero-correlation duration (ZCD) of (0.5N+1) chips is proposed. 2$\^$n/(n=1,2,3) phase ZCD code sets with ZCD and enlarged family sizes are generated by carrying out a chip-shift operation of the preferred pairs . The properties of the proposed codes are effective for the cancellation of MAI and MPI in DS-CDMA Systems.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2002년도 춘계학술발표논문집 (하)
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• pp.1647-1650
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• 2002

In this paper, a class of multi-level spreading codes, i.e., ternary ZCD(zero-correlation duration) spreading codes are introduced. Novel ternary ZCD code sets are generated by carrying out a chip-shift operation of the ternary preferred pairs (TPP) with a ZCD of(0.75N+1)chips. Ternary ZCD codes have superior family size than the binary ZCD codes and they are effective for approximately synchronized (AS) CDMA

• 한국정보과학회논문지:시스템및이론
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• 제33권12호
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• pp.867-879
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• 2006

이 논문에서는 여러 개의 소프트웨어 혹은 하드웨어 컴포넌트가 존재하는 MPSoC(Multiprocessor-System-on-a-chip) 아키텍처를 빠르면서도 정확하게 통합시뮬레이션 하는 내용을 다룬다. 복잡한 시스템을 설계하기 위해서 MPSoC 아키텍처가 점점 일반화되고 있는데, 이러한 아키텍처를 통합시뮬레이션 할 때는 시뮬레이터의 개수가 증가하고 그에 따라 시뮬레이터들 간의 시간 동기화 비용도 증가하므로 전체적인 통합시뮬레이션 성능이 감소된다. 최근의 통합시뮬레이션 연구들에 의해서 등장한 SystemC 통합시뮬레이션 환경이 빠른 성능을 보이고 있으나, 시뮬레이터의 개수가 증가할수록 성능은 반비례한다. 본 논문에서는 효율적인 시간동기를 통해 통합시뮬레이션의 성능을 증가시키는 기법인 가상동기화 기법을 확장하여, (1) SystemC 커널을 수정하지 않고도 가상 동기화 기법을 적용한 SystemC 통합시뮬레이션을 수행할 수 있고, (2) 병렬적으로 가상동기화 기법을 수행할 수 있게 하였다. 이를 통해 SystemC 통합시뮬레이션의 병렬적인 수행이 가능해졌는데, 널리 알려진 상용 SystemC 통합시뮬레이션 도구인 MaxSim과 비교하였을 때, H.263 디코더 예제의 경우 11배 이상의 성능 증가를 얻었고 정확도는 5% 이내로 유지되었다.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2008년도 춘계학술대회 논문집
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• pp.535-544
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• 2008

Unlike MS(Magnetic Stripe), SMART CARD is equipped with COS(Chip Operating System) consisting of the Microprocessor and Memory where information can be stored and processed, and there are two types of cards according to the contact mode; the contact type that passes through a gold plated area and the contactless one that goes through the radio-frequency using an antenna embedded in the plastic card. the contactless IC card used for the transportation card was first introduced into local area buses in Seoul, and expanded throughout the country so that it has removed the inconvenience such as possession of cash, fare payment and collection. Focusing on the Seoul metropolitan area in 2004, prepaid and pay later cards were adopted and have been used interchangeably between a bus and subway. The card terminal compatible between a bus and subway is Proximity Integrated Circuit Card(PICC) as international standards(1443 Type A,B), communicates in the 13.56MHz dynamic frequency modulation-demodulation system, and adopts the Multi Secure Application Module(SAM). In the second half of 2009, the system avaliable nationwide will be built when the payment SAM standard is implemented.

• Journal of Information Processing Systems
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• 제8권1호
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• pp.159-174
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• 2012

This paper presents a study on a high-performance design for a block cipher algorithm implemented on modern many-core graphics processing units (GPUs). The recent emergence of VLSI technology makes it feasible to fabricate multiple processing cores on a single chip and enables general-purpose computation on a GPU (GPGPU). The GPU strategy offers significant performance improvements for all-purpose computation and can be used to support a broad variety of applications, including cryptography. We have proposed an efficient implementation of the encryption/decryption operations of a block cipher algorithm, SEED, on off-the-shelf NVIDIA many-core graphics processors. In a thorough experiment, we achieved high performance that is capable of supporting a high network speed of up to 9.5 Gbps on an NVIDIA GTX285 system (which has 240 processing cores). Our implementation provides up to 4.75 times higher performance in terms of encoding and decoding throughput as compared to the Intel 8-core system.