• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.2
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• pp.38-44
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• 2006

In this paper, a new interference-free Home CDMA-PLC(Code Division Multiple Access-Power Line Communication) system based on the binary ZCD(Zero Correlation Duration) spreading code is proposed as a key solution to overcome the previous problems. Binary ZCD spreading code sets with enlarged family sizes are generated by carrying out a chip-shift operation of the preferred pairs. The properties or the proposed ZCD-PLC systems are effective for MPI(Multi-Path Interference) and MAI (Multiple Access Interference) cancellation in the CDMA-PLC systems. By BER performance simulation, we certified the availability of proposed ZCD-CDMA-PLC system.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.45-50
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• 2012

A family of multi-die DRAM packages was developed that incorporate the full functionality of an SODIMM into a single package. Using a common ball assignment analogous to the edge connector of an SODIMM, a broad range of memory types and assembly structures are supported in this new package. In particular DDR3U, LPDDR3 and DDR4RS are all supported. The center-bonded DRAM use face-down wirebond assembly, while the peripherybonded LPDDR3 use the face-up configuration. Flip chip assembly as well as TSV stacked memory is also supported in this new technology. For the center-bonded devices (DDR3, DDR4 and LPDDR3 ${\times}16$ die) and for the face up wirebonded ${\times}32$ LPDDR3 devices, a simple manufacturing flow is used: all die are placed on the strip in a single machine insertion and are sourced from a single wafer. Wirebonding is also a single insertion operation: all die on a strip are wirebonded at the same time. Because the locations of the power signals is unchanged for these different types of memories, a single consolidated set of test hardware can be used for testing and burn-in for all three memory types.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.9-17
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• 2004

We present a performance improvement of Binary CDMA by flattening the correlation values. A Binary CDMA system, in which multi-leveled transmission signal of multi-code CDMA is clipped into a binary value, is cost-efficient since the strict linearity of the power amplifier is relieved. However, a loss of orthogonality among user channels due to the clipping causes the correlation values at the receiver to have a random distribution. If the correlation value for even a single channel goes too low, the average BER drops considerably. We developed a method of correlation flattening, where the binary chip pattern at the transmitter is adjusted so that the correlation values have averaged magnitude. Experimental results on several spreading codes show that the correlation flattening method increases the number of available channels at reduced BER.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.05a
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• pp.347-352
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• 2004

The author present a modified multi-loop algorithm including feedforward for controlling a 55kW step down chopper in the power supply of Maglev. The control law for the duty cycle consists of three terms. The first is the feedforward term which compensates for variations in the input voltage. The second term consists of the difference between the slowly moving inductor current and output current. The third term consists of proportional and integral terms involving the perturbation in the output voltage. This perturvation is derived by subtracting the desired output voltage from the actual output voltage. The proportional and integral action stabilizes the system and minimizes output voltage error. In order to verify the validity of the proposed multi-loop controller, simulation study was tried using Matlab simulink.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.5_6
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• pp.257-266
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• 2007

In On-Chip bus, the arbitration scheme is one of the critical factors that decide the overall system performance. The arbitration scheme used in traditional shared bus is the master-side arbitration based on the request and grant signals between multiple masters and single arbiter. In the case of the master-side arbitration, only one master and one slave can transfer the data at a time. Therefore the throughput of total bus system and the utilization of resources are decreased in the master-side arbitration. However in the slave-side arbitration, there is an arbiter at each slave port and the master just starts a transaction and waits for the slave response to proceed to the next transfer. Thus, the unit of arbitration can be a transaction or a transfer. Besides the throughput of total bus system and the utilization of resources are increased since the multiple masters can simultaneously perform transfers with independent slaves. In this paper, we implement and analyze the arbitration schemes for the Multi-Layer AHB BusMatrix based on the slave-side arbitration. We implement the slave-side arbitration schemes based on fixed priority, round robin and dynamic priority and accomplish the performance simulation to compare and analyze the performance of each arbitration scheme according to the characteristics of the master and slave. With the performance simulation, we observed that when there are few masters on critical path in a bus system, the arbitration scheme based on dynamic priority shows the maximum performance and in other cases, the arbitration scheme based on round robin shows the highest performance. In addition, the arbitration scheme with transaction based multiplexing shows higher performance than the same arbitration scheme with single transfer based switching in an application with frequent accesses to the long latency devices or memories such as SDRAM. The improvements of the arbitration scheme with transaction based multiplexing are 26%, 42% and 51%, respectively when the latency times of SDRAM are 1, 2 and 3 clock cycles.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.55-60
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• 2017

This paper is proposed on the transmit Method Finger-Printer Scanning of Mutual Capacitance Touch Screen Panel Using Differential Pulse for improving the security of computer information. This system is composed of differential pulse generator and Ring-Counter, also Supply voltage is 5V. this system generates the Pulse wave which is composed of In-Phase and Out of Phase at 1MHz while period of 2m/s. it is designed and be able to operate four channels. overall power consumption is approximately 78.08nW. This prototype is implemented in 0.25um CMOS Process and Chip area is $870um{\times}880um$.

• Ceramist
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• v.21 no.2
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• pp.4-18
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• 2018

Lastly, neuromorphic computing chip has been extensively studied as the technology that directly mimics efficient calculation algorithm of human brain, enabling a next-generation intelligent hardware system with high speed and low power consumption. Three-terminal based synaptic transistor has relatively low integration density compared to the two-terminal type memristor, while its power consumption can be realized as being so low and its spike plasticity from synapse can be reliably implemented. Also, the strong electrical interaction between two or more synaptic spikes offers the advantage of more precise control of synaptic weights. In this review paper, the results of synaptic transistor mimicking synaptic behavior of the brain are classified according to the channel material, in order of silicon, organic semiconductor, oxide semiconductor, 1D CNT(carbon nanotube) and 2D van der Waals atomic layer present. At the same time, key technologies related to dielectrics and electrolytes introduced to express hysteresis and plasticity are discussed. In addition, we compared the essential electrical characteristics (EPSC, IPSC, PPF, STM, LTM, and STDP) required to implement synaptic transistors in common and the power consumption required for unit synapse operation. Generally, synaptic devices should be integrated with other peripheral circuits such as neurons. Demonstration of this neuromorphic system level needs the linearity of synapse resistance change, the symmetry between potentiation and depression, and multi-level resistance states. Finally, in order to be used as a practical neuromorphic applications, the long-term stability and reliability of the synapse device have to be essentially secured through the retention and the endurance cycling test related to the long-term memory characteristics.

• ETRI Journal
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• v.23 no.4
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• pp.177-189
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• 2001

Multicarrier DS-CDMA is an effective approach to combat fading and various kinds of interference. In this paper, we present an overlapped multicarrier DS-CDMA system, wherein each of the rate 1/M convolutionally-encoded symbols is also repetition coded and transmitted using overlapped multicarriers. However, since the frequency spectrums of successive carriers are allowed to overlap, the transmission bandwidth is more efficiently utilized. The effect of the overlapping percentage between successive carriers of a multicarrier DS-CDMA system on the performance is investigated to determine the overlapping percentage showing the best performance. We suggest two methods for sub-band overlapping variation. One is to allow variation of sub-band overlapping percentage when the total number of subcarriers is fixed. The other is to increase the number of sub-bands (the number of repetitions R) with fixed sub-band bandwidth. Given a total number of subcarriers MR, we show that the BER variation is highly dependent on the roll-off factor ${\beta}$ of a raised-cosine chip wave-shaping filter irrespective of convolutional encoding rate 1/M and repetition coding rate 1/R. We also analyze the possibility of reduction in total multi-user interference by considering the variation of both the roll-off factor ($0<{\beta}{\leq}1$) and the sub-band overlapping factor ($0<{\lambda}{\leq}2$), and show that the proposed system may outperform the multicarrier DS-CDMA system in [3].

• Proceedings of the KSRS Conference
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• 2002.10a
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• pp.465-470
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• 2002

A novel phased array antenna system for space-borne polarimetric SAR is proposed and completed in this paper.The antenna system assures polarimetric and multi-mode capability of SAR. It has broadband, high polarization isolation and high port to port isolation. The antenna system is composed of broadband polarimetric microstrip antenna, T/R modules and multifunction beam controller nit. The polarimetric microstrip antenna has more than 100MHz bandwidth at L-band with -30dB polarization isolation and high port to port isolation. The microstrip element and T/R module's structure and characteristics, the subarray's performances measuring results are presented in detail in this paper. A design scheme on beam controller of the phased array antenna is also proposed and completed, which is based on Digital Signal Processing (DSP) chip -TMS320F206. This beam controller unit has small size and high reliability compared with general beam controller. In addition, the multifunction beam controller unit can acquire and then send the T/R module's working states to detection system in real time.

• Proceedings of the IEEK Conference
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• 2000.06a
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• pp.69-72
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• 2000

This paper shows the more improved design of MRI receiver compared to conventional one based on Elscint Spectrometer. At first, the low-cost ADC is 16 bits, 3MHz sampling A/D converter Comparing to conventional one with signal bits of 14 bits, this device with those of 16 bits helps getting Improved the image resolution improved. If frequency is designed centering around 7.6 MHz to be satisfied in 10 MHz of maximum input bandwidth of ADC. For 1st demodulation, fixed IF is used for the purpose of the implementing multi nuclei system. Control parts & partial digital parts are integrated on one chip(FPGA). In DDC(Digital Down Converter), we got required bandwidth of LPF by controlling its decimation rate. With above considerations, we designed optimal receiver for high resolution imaging to be implemented through PC interface & experimental test of receiver of MRI after receiver's fabrication.