• Journal of the Korean Society for Precision Engineering
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• v.28 no.6
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• pp.751-757
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• 2011

Subminiature devices such as Lab-on-a-chip and p-TAS(Micro Total Analysis System) have been intensively studied in biotechnology and chemistry, In many cases, a micromixer was widely used to mix different solutions for synthesizing novel materials. However, in microfluidic system, there is generally a laminar flow under very small Reynolds number so it is difficult to mix each solution perfectly. To settle this problem, we propose a new mixing mechanism which generates a horizontal and vertical multi-mixing (HVM) flow for effective mixing within a short mixing section. We evaluated the proposed mechanism using CFD analysis, and the results showed that the HVM mechanism had a relative high-effectiveness comparing to the existing methods.

• Journal of Semiconductor Engineering
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• v.1 no.1
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• pp.57-63
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• 2020

Complementary metal-oxide-semiconductor (CMOS) technology is now facing a power scaling limit to increase integration density. Since 1970s, multi-valued logic (MVL) has been considered as promising alternative to resolve power scaling challenge for increasing information density up to peta-scale level by reducing the system complexity. Over the past several decades, however, a power-scalable and mass-producible MVL technology has been absent so that MVL circuit and system implementation have been delayed. Recently, compact MVL device researches incorporating multiple-switching characteristics in a single device such as 2D heterojunction-based negative-differential resistance (NDR)/transconductance (NDT) devices and quantum-dot/superlattices-based constant intermediate current have been actively performed. Meanwhile, wafer-scale, energy-efficient and variation-tolerant ternary-CMOS (T-CMOS) technology has been demonstrated through commercial foundry. In this review paper, an overview for MVL development history including recent studies will be presented. Then, the status and its future research direction of MVL technology will be discussed focusing on the T-CMOS technology for peta-scale information processing in semiconductor chip.

• The KIPS Transactions:PartA
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• v.15A no.1
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• pp.61-68
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• 2008

In this paper, we propose the VLSI design of Multi-Format Video Decoder (MFD) to support video codec standards such as MPEG-2, MPEG-4, H.264 and VC-1. The target of the proposed MFD is the Full HD (High Definition) video processing needed for the high-end D-TV SoC (System-on-Chip). The size of the design is reduced by sharing the common large-size resources such as the RISC processor and the on-chip memory among the different codecs. In addition, a detachable architecture is introduced in order to easily add or remove the codecs. The detachable architecture preserves the stability of the previously designed and verified codecs. The size of the design is about 2.4 M gates and the operating clock frequency is 225MHz in the Samsung 65nm process. The proposed MFD supports more than Full-HD (1080p@30fps) video decoding, and the largest number of video codec standards known so far.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1243-1248
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• 2008

As development in technology of bioinformatics recently mates it possible to operate micro-level experiments, we can observe the expression pattern of total genome through on chip and analyze the interactions of thousands of genes at the same time. In this thesis, we used CDNA microarrays of 3840 genes obtained from neuronal differentiation experiment of cortical stem cells on white mouse with cancer. It analyzed and compared performance of each of the experiment result using existing DT, NB, SVM and multi-perceptron neural network classifier combined the similar scale combination method after constructing class classification model by extracting significant gene list with a similar scale combination method proposed in this paper through normalization. Result classifying in Multi-Perceptron neural network classifier for selected 200 genes using combination of PC(Pearson correlation coefficient) and ED(Euclidean distance coefficient) represented the accuracy of 98.84%, which show that it improve classification performance than case to experiment using other classifier.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.3
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• pp.111-117
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• 2018

Heterogeneous multi-core environment integrated with different functional cores is the powerful tool for the embedded system that became more complex and diverse. Specialized application requires one chip solution with different operating system over different cores. But this heterogeneity causes difficult configuration of the development environment, makes hard to develop and test software. We show the environment of heterogeneous multi-core processing can be mapped to symmetric multi-core environment. We construct Linux based RPMsg for the data exchange between processes similar with the heterogeneous multi-core RPMsg and experiment that the proposed environment can be used to reduce the steps of the heterogeneous multi-core application development. With this simplification, we suggest simulation method for easy development and debugging the heterogeneous multicore environment that makes complex steps to simple.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.98-101
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• 1998

The intermodulation distortion(IMD) due to laser diode nonlinearity of an asynhcronous direct sequence code diviion multiple access(DS/CDMA) system in wireless-optical transmission system model is analzed. A third order polynomial is used to represent laser diode nonlinearity. In DS/CDMA system, only one harmonic of the third-order intermodulation term falls on the signal frequency band and influences the system performance characteristics. To cancel multi-user interference and nonlinear distortion in a DS/CDMA wireless-optical transmission system model, the simple transversal filter structure with N-taps of (N-1) tap delay of 1 chip time delay line is used. It is necessary to select an optimal modulation index that provides a maximum signal-to-noise ratio and the results are useful for CDMA system design.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.8
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• pp.172-180
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• 1994

Implantable biotelemetry systems are indispensable tools not only in animal research but also in clinical medicine as such systems enable the acquisition of otherwise unavailable physiological data. We present the manufacture of CMOS IC and its system for implantable multichannel biotelemeter system. The internal circuits of this system are designed not only to achieve as multiple functions and low power dissipation as possible but also to enable continuous measurement of physiological data. Its main functions are to enable continuous measurement of physiological data and to accomplish on-off power swiching of an implantable battery by receiving appropriate commanc signals from an external circuit. The implantable circuits of this system are designed and fabricated on a single silicon chip using $1.5\mu$m n-well CMOS process technology. The total power dissipation of implantable circuits for a continuous operation was 6.7mW and for a stand-by operation was 15.2$\mu$ W. This system used together with approriate sensors is expected to contribute to clinical medicine telemetry system of measuring and wireless transmitting such significant physiological parameters as pressure pH and temperature.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.51 no.2
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• pp.55-60
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• 2002

This paper presents a controller for the multiple DC motors using the CAN(Controller Area Network). The controller has a benefit of reducing the cable connections and making the controller boards compact through the network including expansibility. CAN, among the field buses, is a serial communication methodology which has the physical layer and the data link layer in the ISO's OSI (Open System Interconnect) 7 layered reference model. It provides the user with many powerful features including multi-master functionality and the ability to broadcast / multicast telegrams. When we use a microprocessor chip embedding the CAN function, the system becomes more economical and reliable to react shortly in the data transmission. The controller, we proposed, is composed of two main controllers and a sub controller, which have built with a one-chip microprocessor having CAN function. The sub controller is plugged into the Pentium PC to perform a CAN communication, and connected to the main controllers via the CAN. Main controllers are responsible for controlling two motors respectively. Totally four motors, actuators for the biped robot in our laboratory, are controlled in the experiment. We show that the four motors are controlled properly to actuate the biped robot through the network in real time.

• Journal of Practical Engineering Education
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• v.6 no.2
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• pp.91-97
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• 2014

Education equipment for field programmable gate array (FPGA) based multimedia player design is introduced. Using the education equipment, an example of hardware design for color detection and augment reality (AR) game is described, and an example of syllabus for "Digital system design using FPGA" course is introduced. Using the education equipment, students can develop the ability to design some hardware, and to train the ability for the creative capstone design through conceptual, partial-level, and detail designs. By controlling audio codec, system-on-chip (SOC) design skills combining a NIOS II soft microprocessor and digital hardware in one FPGA chip are improved. The ability to apply wireless communication and LabView to FPGA-based digital design is also increased.

• Journal of KIISE:Software and Applications
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• v.34 no.8
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• pp.697-707
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• 2007

Since embedded software is very dependent for target hardware architecture, characteristics of the platform must be considered when designing the software. Furthermore, MPSoCs consists of heterogeneous hardware components that are specified in micro level. Thus mapping of embedded software for MPSoCs should be considered the characteristics. In this paper, we provide an approach to automatic mapping PIM (Platform Independent Model) of an embedded software to PSM(Platform Specific Model) for MPSoC(Multi Processor System On Chip) and verify its effectiveness with simulation. In the proposed approach, tasks are derived from an object oriented model based on the UML (Unified Modeling Language). And then the types of the derived tasks are identified. With the identified types and inter relationship between tasks, the tasks are assigned to appropriate heterogeneous hardware components. We expect that the approach improve accuracy of the assigning and concurrency of the deployed software.