• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2012년도 추계총회 및 학술대회 논문집
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• pp.71-71
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• 2012

Memory 반도체 Test공정에서 사용되는 Probe Card의 Probing Area가 넓어지면서 종래에 사용되던 Cantilever제품의 사용이 불가능하게 되고, MEMS공정을 사용한 새로운 형태의 Advanced제품이 시장에 출현을 하였다. MEMS형의 제품은 다수의 Micro Spring을 MLC(Multi Layer Ceramic)위에 MEMS 공정을 사용하여 생성하는 방식으로서 MLC는 좁은 지역에 다수의 Pin을 생성 할 수 있는 공간을 만들어 주며, 또 다른 이유는 전기적 특성인 임피던스를 맞추고 다수의 Pin의 압력에 의하여 생기는 하중을 Ceramic기판으로 지탱하기 위한 목적도 있다. 이에 MLC와 같은 전기적 특성을 임피던스를 맞춘 RF-CPCB를 사용하여 작은 면적에 다수의 Pin접합이 가능한 방법을 마련한 후, 이 RF-PCB를 부착하여 Pin의 하중을 받는 Wafer와 유사한 열팽창을 갖는 Substrate를 사용하여 MLC를 대체하여 다양한 온도 조건에서 사용이 가능하며, 복잡하고 공정비가 많이 드는 MEMS 공정에 의한 일괄 Micro Spring 생성 공정을 전주 도금 또는 2D방식의 도금 Pin으로 대체하였으며, Probe Card의 중요한 물리적 특성인 Pin들의 정렬도를 마련하기 위해 Photo Process를 사용한 Wafer로 만든 Wafer Pin Array Frame을 사용하여 2D 제작 Pin을 일괄 또는 부분 접합이 가능한 방법으로 Probe Array Head를 제작하여 이들을 부착하여 Probe Array Head를 이전의 MEMS공정 방법에 비해 쉽고 빠르게 만들어 probe Card를 제작 할 수 있게 되었다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 춘계학술대회 논문집
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• pp.407-408
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• 2006

Almost all injection molds have multi-cavity, which are designed with geometrically balanced runner system in order to made filling balance between cavity to cavity during injection molding. However, filling imbalance has been existed in the geometrically balanced runner system. In this study, we made an experiment and surveyed that are filling balanced variation according to molding condition with thermoplastic vulcanizate (TPV). Also, we conducted experiments in order to know the influence of filling balance for runner core pin (RC pin).

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.791-794
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• 2003

The increasing computational capability of processors is driving the need for high bandwidth links to communicate and store the information that is processed. Such links are often an important part of multi processor interconnection, processor-to-memory interfaces and Serial-network interfaces. This paper describes a 0.11-${\mu}{\textrm}{m}$ CMOS 4 Gbp s/pin 3-Level transceiver using RSL/(Rambus Signaling Logic) for high bandwidth. This system which uses a high-gain windowed integrating receiver with wide common-mode range which was designed in order to improve SNR when operating with the smaller input overdrive of 3-Level. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by low pass effects of channel, process-limited on-chip clock frequency, and serial link distance. In order to detect the transmited 4Gbps/pin with 3-Level data sucessfully ,the receiver is designed using 3-stage sense amplifier. The proposed transceiver employes multi-level signaling (3-Level Pulse Amplitude Modulation) using clock multi phase, double data rate and Prbs patten generator. The transceiver shows data rate of 3.2 ~ 4.0 Gbps/pin with a 1GHz internal clock.

• 오토저널
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• 제15권1호
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• pp.89-99
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• 1993

In this research, important mechanical characteristics of Compliant Press-Fit Pin and PHT are studied through the analysis of deformation mechanisms of Press-Fit Pin and by elastic-plastic finite element method. The direct data for the optimal design of pin was obtained without interfere with the criterion on insertion force and retention force. Also, the insertion force and retention force of new type pin were measured by precision type tensile testing machine and it revealed good agreement with analytical results. In conclusion, it is believed that above results will contribute satisfactorily to the practical design of Press-Fit Pin.

• 한국정밀공학회지
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• 제24권2호
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• pp.41-46
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• 2007

Recently, the study for filling imbalance in thermoplastic polymer has gradually been increased. However, it is hard to find the researches for filling imbalance of thermoplastic elastomer(TPE). The experiment of filling imbalance was conducted for the three kinds of thermoplastic vulcanizes(TPVs) in the mold with geometrically balanced runner system. In this experiment, the effects of the melt temperature and injection speed on the filling imbalance were investigated. To solve the filling imbalance, Runner Core pin(RC pin) in the experimental mold was adopted and it's effects was tested. In this paper, we present that the insert length of RC pin is dependent to each polymers for optimal filling balance.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.165-168
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• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.

• ETRI Journal
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• 제36권2호
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• pp.293-300
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• 2014

As the system-on-chip (SoC) design becomes more complex, the test costs are increasing. One of the main obstacles of a test cost reduction is the limited number of test channels of the ATE while the number of pins in the design increases. To overcome this problem, a new test architecture using a channel sharing compliant with IEEE Standard 1149.1 and 1500 is proposed. It can significantly reduce the pin count for testing a SoC design. The test input data is transmitted using a test access mechanism composed of only input pins. A single test data output pin is used to measure the sink values. The experimental results show that the proposed architecture not only increases the number of sites to be tested simultaneously, but also reduces the test time. In addition, the yield loss owing to the proven contact problems can be reduced. Using the new architecture, it is possible to achieve a large test time and cost reduction for complex SoC designs with negligible design and test overheads.

• 한국정밀공학회지
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• 제29권2호
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• pp.139-146
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• 2012

A multi-tasking machine tool for large scale marine engine crankshafts has been developed together with design technologies for its special devices. Since work pieces, that is, crankshafts to be machined are big and heavy; weight of over 100 tons, length of 10 m long, and diameter of over 3.5 m, several special purpose core devices are necessarily developed such as PTD (Pin Turning Device) for machining eccentric pin parts, face place and steady rest for chucking and resting heavy work pieces. PTD is a unique special purpose device of open-and-close ring typed structure equipped with revolving ring spindle for machining eccentric pins apart from journal. In order to achieve high rigidity of the machine tool, structural design optimization using TMSA (Taguch Method based Sequential Algorithm) has been completed with FEM structural analysis, and a hydrostatic bearing system for the PTD has been developed with theoretical hydrostatic analysis.

• Composites Research
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• 제18권6호
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• pp.9-18
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• 2005

복합재료가 항공기 구조물 및 기계부품 등에 폭 넓게 적용됨에 따라, 복합재료 구조물에서 가장 취약한 복합재료 체결부의 설계는 매우 중요한 연구 분야로 대두되고 있다. 본 논문에서는 기계적으로 체결이 된 단일 및 다중 핀 하중을 받는 복합재료 평판에서 응력분포에 대한 해석적인 연구를 수행하였다. 또한, 기계적체결부인 핀과 구멍간에서 접촉 문제를 다루기 위하여 접촉응력해석을 이용한 유한요소 모델이 사용되었으며, 응력분포를 정량적으로 비교하기 위하여 무차원화한 응력집중계수를 이용하였다. 단일 핀 하중을 받는 경우에 대하여 적층순서, 원공의 지름에 대한 평판 폭의 비 (W/D ratio), 원공의 지름에 대한 끝단에서 원공까지의 길이의 비 (En ratio), 마찰계수, 와셔의 조임력 등에 대한 영향을 알아보았으며, 다중 핀 하중을 받는 경우에 응력집중계수를 이용하여 핀의 개수, 피치, 열의 개수, 열 간격 및 원공의 배치형상의 영향에 대하여 알아보았다. 단일 핀 하중을 받는 경우에 대한 결과로부터, DBLT (Double-Bias-Longitudinal Transverse) 복합재료 평판에서 응력이 가장 민감하게 나타나는 것을 알 수 있었고, 원공의 지름에 대한 평판 폭의 비와끝단에서 원공까지의 길이의 비에 따른 응력의 변화가 민감하게 나타나는 것을 확인할 수 있었다. 또한, 다중핀 하중을 받는 경우에 대한 응력해석의 결과로부터, 원공이 2열로 배치된 복합재료 평판에서 응력집중현상이 가장 적게 일어나는 것을 확인하였다. 이러한 해석을 통하여, 체결부에서 나타나는 응력분포로부터 복합재료 평판에서의 파손형태를 예측할 수 있다.

• Nuclear Engineering and Technology
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• 제56권3호
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• pp.980-992
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• 2024

Steam line break accident (SLB) in the nuclear reactor is one of the representative Non-LOCA accidents in which thermal-hydraulics and neutron kinetics are strongly coupled each other. Thus, the multi-scale and multi-physics approach is applied in this study in order to examine a realistic safety margin. An entire reactor coolant system is modelled by system scale node, whereas sub-channel scale resolution is applied for the region of interest such as the reactor core. Fuel performance code is extended to consider full core pin-wise fuel behaviour. The MARU platform is developed for easy integration of the codes to be coupled. An initial stage of the steam line break accident is simulated on the MARU platform. As cold coolant is injected from the cold leg into the reactor pressure vessel, the power increases due to the moderator feedback. Three-dimensional coolant and fuel behaviour are qualitatively visualized for easy comprehension. Moreover, quantitative investigation is added by focusing on the enhancement of safety margin by means of comparing the minimum departure from nucleate boiling ratio (MDNBR). Three factors contributing to the increase of the MDNBR are proposed: Various geometric parameters, realistic power distribution by neutron kinetics code, Radial coolant mixing including sub-channel physics model.