• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.7
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• pp.560-570
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• 2013

In this paper, we propose transceiver design strategies for the two-cell multiple-input multiple-output (MIMO) interfering broadcast channel where inter-cell interference (ICI) exists in addition to inter-user interference (IUI). We first formulate the generalized zero-forcing interference alignment (ZF-IA) method based on the alignment of IUI and ICI in multi-dimensional subspace. We then devise a minimum weighted-mean-square-error (WMSE) method based on "regularizing" the precoders and decoders of the generalized ZF-IA scheme. In contrast to the existing weighted-sum-rate-maximizing transceiver, our method does not require an iterative calculation of the optimal weights. Because of this, the proposed scheme, while not designed specially to maximize the sum-rate, is computationally efficient and achieves a faster convergence compared to the known weighed-sum-rate maximizing scheme. Through analysis and simulation, we show the effectiveness of the proposed regularized ZF-IA scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.75-84
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• 2004

In this paper, we proposed an efficient hardware architecture of line-based lifting algorithm for Motion JPEG2000. We proposed a new architecture of a lifting-based filtering cell which has an optimized and simplified structure. It was implemented in a hardware accommodating both (9,7) and (5,4) filter. Since the output rate is linearly proportional to the input rate, one can obtain the high throughput through parallel operation simply by adding the hardware units. It was implemented into both of ASIC and FPGA The 0.35${\mu}{\textrm}{m}$ CMOS library from Samsung was used for ASIC and Altera was the target for FRGA. In ASIC, the proposed architecture used 41,592 gates for the lifting arithmetic and 128 Kbit memory. For FPGA it used 6,520 LEs(Logic Elements) and 128 ESBs(Embedded System Blocks). The implementations were stably operated in the clock frequency of 128MHz and 52MHz, respectively.

• Journal of the Korea Convergence Society
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• v.3 no.4
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• pp.35-44
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• 2012

In this study, a simulation program is developed in order to investigate non steady-state cornering performance of 6WD/6WS special-purpose vehicles. 6WD vehicles are believed to have good performance on off-the-road maneuvering and to have fail-safe capabilities. But the cornering performances of 6WS vehicles are not well understood in the related literature. In this paper, 6WD/6WS vehicles are modeled as a 18 DOF system which includes non-linear vehicle dynamics, tire models, and kinematic effects. Then the vehicle model is constructed into a simulation program using the MATLAB/SIMULINK so that input/output and vehicle parameters can be changed easily with the modulated approach. Cornering performance of the 6WS vehicle is analyzed for brake steering and pivoting, respectively. Simulation results show that cornering performance depends on the middle-wheel steering as well as front/rear wheel steering. In addition, a new 6WS control law is proposed in order to minimize the sideslip angle. Lane change simulation results demonstrate the advantage of 6WS vehicles with the proposed control law.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.963-972
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• 2002

An 8192-point pipelined FFT/IFFT processor core is designed, which can be used in multi-carrier modulation systems such as DUf-based VDSL modem and OFDM-based DVB system. In order to improve the signal-to-quantization-noise ratio (SQNR) of FFT/IFFT results, two-step convergent block floating-point (TS_CBFP) scaling is employed. Since the proposed TS_CBFP scaling does not require additional buffer memory, it reduces memory as much as about 80% when compared with conventional CBFP methods, resulting in area-and power-efficient implementation. The SQNR of about 60-㏈ is achieved with 10-bit input, 14-bit internal data and twiddle factors, and 16-bit output. The core synthesized using 0.25-$\mu\textrm{m}$ CMOS library has about 76,300 gates, 390K bits RAM, and twiddle factor ROM of 39K bits. Simulation results show that it can safely operate up to 50-㎒ clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. It was verified by Xilinx FPGA implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.10A
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• pp.776-783
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• 2009

Current-cut circuit is an effective method to obtain low power consumption in wireless communication systems as high speed OFDM. For the operation of current-mode FFT LSI with analog signal processing essentially requires current-mode serial-to-parallel/parallel-to-serial converter with multi input and output structure. However, the Hold-mode operation of current-mode serial-to-parallel/parallel-to-serial converter has unnecessary power consumption. We propose a novel current-mode serial-to-parallel/parallel-to-serial converter with current-cut circuit and full chip simulation results agree with experimental data of low power consumption. The proposed current-mode serial-to-parallel/parallel-to-serial converter promise the wide application of the current-mode analog signal processing in the field of low power wireless communication LSI.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.11 s.114
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• pp.1058-1064
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• 2006

In this paper, the channel capacity of a specified wireless indoor multiple-input multiple-output(MIMO) channel is estimated by analyzing spatial characteristics of this channel using the three-dimensional ray tracing method, and a technique for deriving an optimized separation of multi-antenna elements is proposed. At first, the ray paths, the path losses, and the time-delay profile are computed using the three-dimensional ray tracing method in an indoor corridor environment, which has the line of sight(LOS) and non-line of sight(NLOS) regions. The ray tracing method is verified by a comparison between the computation results and the measurements which are obtained with dipole antennas, an amplifier and a network analyzer. Then, an MIMO system is positioned in the indoor channel environment and the ray paths and path losses are computed for four antenna-position combinations and various values of the antenna separation to obtain the channel capacity for the MIMO system. An optimum antenna-separation is derived by averaging the channel capacities of 100 receiver positions with four different antenna combinations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.1095-1101
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• 2012

This paper presents a design of a BLDC servo motor control system for the auto process of assembly and supply using DSP(Digital Signal Processor) controller and IGBT driver. The assembly and supply auto processing system needs torque, speed, position control of servo motor for variable action. This paper implements those servo control with vector control and space vector PWM(Pulse Width Modulation) technique. As CPU of controller, TMS320F240 DSP was adopted because it has PWM waveform generator, A/D converter, SPI(Serial Peripheral Interface) port and many input/output port etc. This control system consists of 3-level hierarchy structure that main host PC manages three sub DSP system which transfer downward command and are monitoring the states of end servo controllers. Each sub DSP system operates eight BLDC servo controllers which control BLDC motor using DSP and IPM. Between host system and sub DSP communicate with RS-422, between main processor and controller communicate with SPI port.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.9
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• pp.1010-1019
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• 2016

The K-user multiple-input single-output broadcast channel is considered under per-antenna power constraints, i. e., each transmit antenna must satisfy its own power constraints. A low complexity zeroforcing(ZF) precoder is proposed when the number of transmit antennas M is greater than K. The proposed precoder design significantly reduces computational complexity for the precoder construction while attaining the sum spectral efficiency close to that achievable by the optimal ZF precoder.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.11
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• pp.2008-2013
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• 2006

In numerical analysis on evaluating the thermal performance of the thermal equipment, numerical values of thermodynamic properties such as temperature, pressure, specific volume, enthalpy and entropy are required. But the steam table itself cannot be used without modelling. In this study applicability of neural networks in modelling the wide temperature range of wet saturated vapor region was examined. the multi-layer neural network consists of a input layer with 1 node, two hidden layers with 10 and 20 nodes respectively and a output layer with 6 nodes. Quadratic and cubic spline interpoations methods were also applied for comparison. Neural network model revealed similar percentage error to spline interpolation. From these results, it is confirmed that the neural networks could be powerful method in modelling the wide range of the steam table.

• KIPS Transactions on Computer and Communication Systems
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• v.5 no.12
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• pp.439-446
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• 2016

In this paper, an efficient prediction accuracy enhancement strategy is proposed for improving the performance of the prediction-based parallel event-driven gate-level timing simulation. The proposed new strategy adopts the static double prediction and the dynamic prediction for input and output values of local simulations. The double prediction utilizes another static prediction data for the secondary prediction once the first prediction fails, and the dynamic prediction tries to use the on-going simulation result accumulated dynamically during the actual parallel simulation execution as prediction data. Therefore, the communication overhead and synchronization overhead, which are the main bottleneck of parallel simulation, are maximally reduced. Throughout the proposed two prediction enhancement techniques, we have observed about 5x simulation performance improvement over the commercial parallel multi-core simulation for six test designs.