• Title/Summary/Keyword: Multi-Chip Packaging

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Conceptual Design of Multi-Functional Structure using Rectangular Grid-Stiffened Structure for Satellite (위성용 사각형 격자강화 구조의 다기능 구조체 개념설계)

  • Seo, Hyun-Suk;Jang, Tae-Seong;Rhee, Ju-Hun;Kim, Won-Seock;Hyun, Bum-Seok;Lim, Jae-Hyuk;Hwang, Do-Soon;Lee, Sang-Kon;Cho, Hee-Keun;Han, Eun-Soo;Kim, Im-Soo;Sim, Eun-Sup
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.39 no.6
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    • pp.526-534
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    • 2011
  • The MFS (Mlti-Functional Structure) concept, which integrates the electronics, thermal control and structure into a single packaging system, has been developed and applied to reduce the volume and weight of the satellite. Therefore, this MFS can eliminate the bulky chassis/frames, cables and connectors of the electronic equipment. The main point of this traditional MFS is the replacement of the electrical chassis/frames with MCMs (Multi-Chip Modules) that require much costs and efforts for developing. This paper shows the new MFS concept that effectively saves the volume and weight. The structure including the thermal control and radiation shielding elements will be designed and manufactured as the rectangular grid-stiffened structure. The rectangular grid-stiffened structure is the modification of the iso-grid structure, and provides the enough spaces for putting the general PCBs without the chassis/frames.

Wavelet Transform Based Doconvolution of Ultrasonic Pulse-Echo Signal (웨이브렛 변환을 이용한 초음파 펄스 에코 신호의 디컨볼루션)

  • Jhang, Kyung-Young;Jang, Hyo-Seong;Park, Byung-Yll;Ha, Job
    • Journal of the Korean Society for Nondestructive Testing
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    • v.20 no.6
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    • pp.511-520
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    • 2000
  • Ultrasonic pulse echo method comes to be difficult to apply to the multi-layered structure with very thin layer, because the echoes from the top and the bottom of the layer are superimposed. We can easily meet this problem when the silicon chip layer in the semiconductor is inspected by a SAM equipment using fairly low frequency lower than 20MHz by which severe attenuation in the epoxy mold compound of packaging material can be overcome. Conventionally, deconvolution technique has been used for the decomposition of superimposed UT signals, however it has disabilities when the waveform of the transmitted signal is distorted according to the propagation. In this paper, the wavelet transform based deconvolution(WTBD) technique is proposed as a new signal processing method that can decompose the superimposed echo signals with superior performances compared to the conventional deconvolution technique. WTBD method uses the wavelet transform in the pre-stage of deconvolution to extract out the common waveform from the transmitted and received signal with distortion. Performances of the proposed method we shown by through computer simulations using model signal with noise and we demonstrated by through experiments for the fabricated semiconductor sample with partial delamination at the top of silicon chip layer.

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Fabrication and Characterization of Low Noise Amplifier using MCM-C Technology (MCM-C 기술을 이용한 저잡음 증폭기의 제작 및 특성평가)

  • Cho, H.M.;Lim, W.;Lee, J.Y.;Kang, N.K.;Park, J.C.
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2000.11a
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    • pp.61-64
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    • 2000
  • We fabricated and characterized Low Noise Amplifier (LNA) using MCM-C (Multi-Chip-Module-Cofired) technology for 2.14 GHz IMT-2000 mobile terminal application. First, We designed LNA circuits and simulated it's high frequency characteristics using circuits simulator. For the simulation, we adopted high frequency libraries of all the devices used in LNA samples. By the simulation, Gain was 17 dB and Noise Figure was 1.4 dB. We used multilayer process of LTCC (Low Temperature Co-fired Ceramics) substrate and conductor, resistor pattern for the MCM-C LNA fabrication. We made 2 buried inductors, 2 buried capacitors and 3 buried resistors. The number of the total layers was 6. On the top layer, we patterned microstrip line and pads for the SMT device. We measured the high frequency characteristics, and the results were 14.7 dB Gain and 1.5 dB Noise Figure.

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The Design of 2.4 GHz Band LTCC Bandpass Filter using $\lambda$/4 Hairpin Resonators ($\lambda$/4 Hairpin 공진기를 이용한 2.4 GHz 대역 LTCC 대역통과 필터의 설계)

  • Sung Gyu-Je
    • Journal of the Microelectronics and Packaging Society
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    • v.11 no.4 s.33
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    • pp.7-11
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    • 2004
  • In this paper, a $\lambda$/4 hairpin resonator is applied to reduce the size of planar resonators for a 2.4 GHz Band LTCC MLC bandpass filter. The $\lambda$/4 hairpin resonator operates as stepped impedance resonator (SIR) without changing the width of the planar resonator. It is composed of two sections those are parallel coupled line and transmission line. The characteristic impedance of two sections is different each other. The design formulas of the bandpass filter using the coupling element at the arbitrary position are derived from even and odd-mode analysis. The formulas can take account of the arbitrary coupling of lumped and/or distributed resonators. The advantage of this filter is its abilities to change freely the coupling structure between two resonators. Experimental bandpass filters for 2.4 GHz Band are implemented and their performances are shown.

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Properties and Curing Behaviors of UV Curable Adhesives with Different Coating Thickness in Temporary Bonding and Debonding Process (Temporary Bonding and Debonding 공정용 UV 경화형 접착 소재의 코팅 두께에 따른 물성 및 경화거동)

  • Lee, Seung-Woo;Lee, Tae-Hyung;Park, Ji-Won;Park, Cho-Hee;Kim, Hyun-Joong
    • Journal of the Korean Society for Precision Engineering
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    • v.31 no.10
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    • pp.873-879
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    • 2014
  • UV curable adhesives with different acrylic functionalities were synthesized for temporary bonding and debonding process in 3D multi-chip packaging process. The aim is to study various factors which have an influence on UV curing. The properties and curing behaviors were investigated by gel fraction, peel strength, probe tack, and shear adhesion failure temperature. The results show that the properties and curing behaviors are dependent on not only acrylic functionalities of binders but also UV doses and coating thickness.

A Study on the Design and Characteristics of thin-film L-C Band Pass Filter

  • Kim In-Sung;Song Jae-Sung;Min Bok-Ki;Lee Won-Jae;Muller Alexandru
    • KIEE International Transactions on Electrophysics and Applications
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    • v.5C no.4
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    • pp.176-179
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    • 2005
  • The increasing demand for high density packaging technologies and the evolution to mixed digital and analogue devices has been the con-set of increasing research in thin film multi-layer technologies such as the passive components integration technology. In this paper, Cu and TaO thin film with RF sputtering was deposited for spiral inductor and MOM capacitor on the $SiO_2$/Si(100) substrate. MOM capacitor and spiral inductor were fabricated for L-C band pass filter by sputtering and lift-off. We are analyzed and designed thin films L-C passive components for band pass filter at 900 MHz and 1.8 GHz, important devices for mobile communication system. Based on the high-Q values of passive components, MOM capacitor and spiral inductors for L-C band pass filter, a low insertion loss of L-C passive components can be realized with a minimized chip area. The insertion loss was 3 dB for a 1.8 GHz filter, and 5 dB for a 900 MHz filter. This paper also discusses a analysis and practical design to thin-film L-C band pass filter.

Thermal Analysis of 3D package using TSV Interposer (TSV 인터포저 기술을 이용한 3D 패키지의 방열 해석)

  • Suh, Il-Woong;Lee, Mi-Kyoung;Kim, Ju-Hyun;Choa, Sung-Hoon
    • Journal of the Microelectronics and Packaging Society
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    • v.21 no.2
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    • pp.43-51
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    • 2014
  • In 3-dimensional (3D) integrated package, thermal management is one of the critical issues due to the high heat flux generated by stacked multi-functional chips in miniature packages. In this study, we used numerical simulation method to analyze the thermal behaviors, and investigated the thermal issues of 3D package using TSV (through-silicon-via) technology for mobile application. The 3D integrated package consists of up to 8 TSV memory chips and one logic chip with a interposer which has regularly embedded TSVs. Thermal performances and characteristics of glass and silicon interposers were compared. Thermal characteristics of logic and memory chips are also investigated. The effects of numbers of the stacked chip, size of the interposer and TSV via on the thermal behavior of 3D package were investigated. Numerical analysis of the junction temperature, thermal resistance, and heat flux for 3D TSV package was performed under normal operating and high performance operation conditions, respectively. Based on the simulation results, we proposed an effective integration scheme of the memory and logic chips to minimize the temperature rise of the package. The results will be useful of design optimization and provide a thermal design guideline for reliable and high performance 3D TSV package.

Numerical Analysis of Warpage and Stress for 4-layer Stacked FBGA Package (4개의 칩이 적층된 FBGA 패키지의 휨 현상 및 응력 특성에 관한 연구)

  • Kim, Kyoung-Ho;Lee, Hyouk;Jeong, Jin-Wook;Kim, Ju-Hyung;Choa, Sung-Hoon
    • Journal of the Microelectronics and Packaging Society
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    • v.19 no.2
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    • pp.7-15
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    • 2012
  • Semiconductor packages are increasingly moving toward miniaturization, lighter and multi-functions for mobile application, which requires highly integrated multi-stack package. To meet the industrial demand, the package and silicon chip become thinner, and ultra-thin packages will show serious reliability problems such as warpage, crack and other failures. These problems are mainly caused by the mismatch of various package materials and geometric dimensions. In this study we perform the numerical analysis of the warpage deformation and thermal stress of 4-layer stacked FBGA package after EMC molding and reflow process, respectively. After EMC molding and reflow process, the package exhibits the different warpage characteristics due to the temperature-dependent material properties. Key material properties which affect the warpage of package are investigated such as the elastic moduli and CTEs of EMC and PCB. It is found that CTE of EMC material is the dominant factor which controls the warpage. The results of RSM optimization of the material properties demonstrate that warpage can be reduced by $28{\mu}m$. As the silicon die becomes thinner, the maximum stress of each die is increased. In particular, the stress of the top die is substantially increased at the outer edge of the die. This stress concentration will lead to the failure of the package. Therefore, proper selection of package material and structural design are essential for the ultra-thin die packages.

Numerical Study of Warpage and Stress for the Ultra Thin Package (수치해석에 의한 초박형 패키지의 휨 현상 및 응력 특성에 관한 연구)

  • Song, Cha-Gyu;Choa, Sung-Hoon
    • Journal of the Microelectronics and Packaging Society
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    • v.17 no.4
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    • pp.49-60
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    • 2010
  • Semiconductor packages are increasingly moving toward miniaturization, lighter and high performance. Futhermore, packages become thinner. Thin packages will generate serious reliability problems such as warpage, crack and other failures. Reliability problems are mainly caused by the CTE mismatch of various package materials. Therefore, proper selection of the package materials and geometrical optimization is very important for controlling the warpage and the stress of the package. In this study, we investigated the characteristics of the warpage and the stress of several packages currently used in mobile devices such as CABGA, fcSCP, SCSP, and MCP. Warpage and stress distribution are analyzed by the finite element simulation. Key material properties which affect the warpage of package are investigated such as the elastic moduli, CTEs of EMC molding and the substrate. Geometrical effects are also investigated including the thickness or size of EMC molding, silicon die and substrate. The simulation results indicate that the most influential factors on warpage are EMC molding thickness, CTE of EMC, elastic modulus of the substrate. Simulation results show that warpage is the largest for SCSP. In order to reduce the warpage, DOE optimization is performed, and the optimization results show that warpage of SCSP becomes $10{\mu}m$.

Study on Sn-Ag-Fe Transient Liquid Phase Bonding for Application to Electric Vehicles Power Modules (전기자동차용 파워모듈 적용을 위한 Sn-Ag-Fe TLP (Transient Liquid Phase) 접합에 관한 연구)

  • Byungwoo Kim;Hyeri Go;Gyeongyeong Cheon;Yong-Ho Ko;Yoonchul Sohn
    • Journal of the Microelectronics and Packaging Society
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    • v.30 no.4
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    • pp.61-68
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    • 2023
  • In this study, Sn-3.5Ag-15.0Fe composite solder was manufactured and applied to TLP bonding to change the entire joint into a Sn-Fe IMC(intermetallic compound), thereby applying it as a high-temperature solder. The FeSn2 IMC formed during the bonding process has a high melting point of 513℃, so it can be stably applied to power modules for power semiconductors where the temperature rises up to 280℃ during use. As a result of applying ENIG surface treatment to both the chip and substrate, a multi-layer IMC structure of Ni3Sn4/FeSn2/Ni3Sn4 was formed at the joint. During the shear test, the fracture path showed that cracks developed at the Ni3Sn4/FeSn2 interface and then propagated into FeSn2. After 2hours of the TLP joining process, a shear strength of over 30 MPa was obtained, and in particular, there was no decrease in strength at all even in a shear test at 200℃. The results of this study can be expected to lead to materials and processes that can be applied to power modules for electric vehicles, which are being actively researched recently.