• Magazine of the Korean Society of Agricultural Engineers
• /
• v.42 no.2
• /
• pp.71-77
• /
• 2000

A multi-region model for solute transport through saturated soils has been developed to describe preferential flow. The model consists of numerous discrete pore groups, which are characterized by a discrete dispersion coefficient, flow velocity, and porosity . The hydraulic properties for each pore group are derived from a soil's hydraluic conductivity and soil water characteristic functions . Flow in pore group is described by the classical advection-disersion equation (ADE). An implict finite difference scheme was applied to the governing equation that results in a block-tridiagonal system of equations that is very efficient and allows the soil to be divided into any number of pore groups. The numerical technique is derived from methods used to solve coupled equations in fluid dynamics problems and can also be applied to the transport of interacting solutes. The results of the model are compared to the experimental data from published papers. This paper contributes on the characteristics of the method when applied to the parallel porosity model to describe preferential flow of solutes in soil.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.6
• /
• pp.1355-1362
• /
• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. Our LDPC decoder adopts a block-serial architecture based on min-sum algorithm and layered decoding scheme. A novel way to store check-node values and parity check matrix reduces the sizes of check-node memory and H-ROM. An efficient scheme for check-node memory addressing is used to achieve stall-free read/write operations. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.12
• /
• pp.3-11
• /
• 2014

Multiple antennas can provide huge capacity gains when the transmitter knows the channel state information (CSI). Precoding is a technique that exploits CSI at the transmitter side. In this paper, an adaptive precoding scheme is proposed, called a hybrid multiple-input multiple-output (MIMO) precoding (HMP). HMP is a combination of linear and nonlinear precoding. The number of transmit antennas less than or equal to four is as same as the conventional antenna selection scheme. Therefore, the HMP scheme uses more than four transmit antennas. The good channel means that the channels must be selected to maximize the channel capacity among the given channels, and the rest channels are called bad channel. In HMP scheme, we use the nonlinear precoding in the good channels and the linear precoding in the bad channels. The well-known Tomlinson-Harashima precoding (THP) is considered as nonlinear precoding. The system throughput and MSE (minimum square error) are shown for the performance of HMP scheme compared to the conventional schemes which are BD (block diagonalization), antenna selection and THP.

• Journal of Communications and Networks
• /
• v.16 no.6
• /
• pp.592-599
• /
• 2014

Cloud computing enables users to easily store their data and simply share data with others. Due to the security threats in an untrusted cloud, users are recommended to compute verification metadata, such as signatures, on their data to protect the integrity. Many mechanisms have been proposed to allow a public verifier to efficiently audit cloud data integrity without receiving the entire data from the cloud. However, to the best of our knowledge, none of them has considered about the efficiency of public verification on multi-owner data, where each block in data is signed by multiple owners. In this paper, we propose a novel public verification mechanism to audit the integrity of multi-owner data in an untrusted cloud by taking the advantage of multisignatures. With our mechanism, the verification time and storage overhead of signatures on multi-owner data in the cloud are independent with the number of owners. In addition, we demonstrate the security of our scheme with rigorous proofs. Compared to the straightforward extension of previous mechanisms, our mechanism shows a better performance in experiments.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.40 no.2
• /
• pp.56-63
• /
• 2003

We investigate some implementation factors that affect the performance of multi-rate parallel interference cancellers (PICs) for the international mobile telecommunications-2000 (IMT-2000) 3rd-generation partnership project (3GPP) system. We consider the simple multi-rate PIC [1,2] that can remove effectively multiple access interference (MAI) through block-based detection and sample-based cancellation in asynchronous user environments. The PIC structure has significantly lower complexity as compared with that of the existing scheme, especially as the number of users increases. We analyze the effects of timing error, oversampling rate, unsynchronized users and/or outer-cell interference, and the number of Quantization bits on the PIE performance through extensive computer simulations. The models for such factors and the optimum parameters are drawn. Finally, we evaluate the receiver complexities of the PIC receivers employing using the advanced removal scheme.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.2
• /
• pp.363-371
• /
• 2013

This paper describes a multi-standard LDPC decoder which supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard and 3 block lengths(648, 1296, 1944) and 4 code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A DFU(decoding function unit) based on sign-magnitude arithmetic is used for hardware reduction. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.13-${\mu}m$ CMOS cell library. It has 312,000 gates and 70,000 bits RAM. The estimated throughput is about 79~210 Mbps at 100 MHz@1.8v.

• Journal of Broadcast Engineering
• /
• v.14 no.5
• /
• pp.601-615
• /
• 2009

This paper proposes an efficient depth-map coding method for generating virtual-view images in 3D-Video. Virtual-view images can be generated by the view-interpolation based on the depth-map of the image. A conventional video coding method such as H.264 has been used. However, a conventional video coding method does not consider the image characteristics of the depth-map. Therefore, this paper proposes an adaptive depth-map coding method that can select between the H.264/AVC coding scheme and the proposed gray-coded bit plane-based coding scheme in a unit of block. This improves the coding efficiency of the depth-map data. Simulation results show that the proposed method, in comparison with the H.264/AVC coding scheme, improves the average BD-rate savings by 7.43% and the average BD-PSNR gains by 0.5dB. It also improves the subjective picture quality of synthesized virtual-view images using decoded depth-maps.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.1
• /
• pp.36-42
• /
• 2016

In multi-level-cell based storage devices, TLC NAND has been employed solid state drive due to cost effectiveness. Since TLC has slow performance and low endurance compared with MLC, TLC based storage has adopted SLC buffer scheme to improve performance. To improve SLC buffer scheme, this paper proposes page overwriting method in SLC block. This method provides data updates without erase operation within a limited number. When SLC buffer area is filled up, FTL should execute copying valid pages and erasing it. The proposed method reduces erase counts by 50% or more compared with previous SLC buffer scheme. Simulation results show that the proposed SLC buffer overwrite method achieves 2 times write performance improvement.

• Journal of KIISE:Databases
• /
• v.29 no.4
• /
• pp.262-273
• /
• 2002

MOLAP is a technology that accelerates multidimensional data analysis by storing data in a multidimensional array and accessing them using their position information. Depending on a mapping scheme of a multidimensional array onto disk, the sliced of MOLAP operations such as slice and dice varies significantly. [1] proposed a MOLAP cube storage scheme that divides a cube into small chunks with equal side length, compresses sparse chunks, and stores the chunks in row-major order of their chunk indexes. This type of cube storage scheme gives a fair chance to all dimensions of the input data. Here, we developed a variant of their cube storage scheme by placing chunks in a different order. Our scheme accelerates slice and dice operations by aligning chunks to physical disk block boundaries and clustering neighboring chunks. Z-indexing is used for chunk clustering. The efficiency of the proposed scheme is evaluated through experiments. We showed that the proposed scheme is efficient for 3~5 dimensional cubes that are frequently used to analyze business data.

• Journal of Communications and Networks
• /
• v.18 no.3
• /
• pp.420-428
• /
• 2016

In this paper, we investigate the scheduling and power allocation for coordinated multi-point transmission in downlink long term evolution advanced (LTE-A) systems, where orthogonal frequency division multiple-access is used. The proposed scheme jointly optimizes user selection, power allocation, and modulation and coding scheme (MCS) selection to maximize the weighted sum throughput with fairness consideration. Considering practical constraints in LTE-A systems, the MCSs for the resource blocks assigned to the same user need to be the same. Since the optimization problem is a combinatorial and non-convex one with high complexity, a low-complexity algorithm is proposed by separating the user selection and power allocation into two subproblems. To further simplify the optimization problem for power allocation, the instantaneous signal-to-interference-plus-noise ratio (SINR) and the average SINR are adopted to allocate power in a single cell and multiple coordinated cells, respectively. Simulation results show that the proposed scheme can improve the average system throughput and the cell-edge user throughput significantly compared with the existing schemes with limited feedback.