• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.615-628
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• 2015

CGRA (Coarse-Grained Reconfigurable Architecture) based multi-core architecture can be considered as a suitable solution for the fault-tolerant computing. However, there have been a few research projects based on fault-tolerant CGRA without exploiting the strengths of CGRA as well as their works are limited to single CGRA. Therefore, in this paper, we propose two approaches to enable exploiting the inherent redundancy and reconfigurability of the multi-CGRA for fault-recovery. One is a resilient inter-CGRA fabric that is ring-based sharing fabric (RSF) with minimal interconnection overhead. Another is a novel intra/inter-CGRA reconfiguration technique on RSF for maximizing utilization of the resources when faults occur. Experimental results show that the proposed approaches achieve up to 94% faulty recoverability with reducing area/delay/power by up to 15%/28.6%/31% when compared with completely connected fabric (CCF).

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.706-709
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• 2005

Despite geometrical balanced runner system, filling imbalances between cavity to cavity have always been observed in multi-cavity injection mold. These filling imbalances are results from non-symmetrical shear rate distribution within melt as it flows through the runner system. It has been possible to decrease filling imbalance by optimizing processing conditions, but it has not completely eliminated this phenomenon during the injection molding processing. This paper presents a solution of these filling imbalances by using runner core pin which creates a symmetrical shear distribution within runner and the effects on filling imbalance when modifying a shape of runner core pin. As a result of using runner core pin, a remarkable improvement in reducing filling imbalance was confirmed. In addition we investigated how filling imbalances were affected by shape of runner core pin.

• Journal of Adhesion and Interface
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• v.14 no.1
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• pp.1-12
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• 2013

Multi core-shell composite particles were prepared by the water-born emulsion polymerization of various core monomers such as methyl methacrylate (MMA), ethyl methacrylate (EMA) and shell monomers such as MMA, EMA, 2-hydroxyl ethyl methacrylate (2-HEMA), glycidyl methacrylate (GMA) and methacrylic acid (MAA) in the presence of different concentrations of sodium dodecyl benzene sulfonate (SDBS). The following conclusions are drawn from the conversion, particle size and distribution, average molecular weight, molecular structure, glass transition temperature with DSC, contact angle after plasma treatment, tensile strength and isothermal decomposition kinetics. In the case of the concentration of 0.02 wt% SDBS, the conversion of MMA core-(EMA/GMA) shell composite particles was excellent as 98.5%. In the case of the concentration of 0.03 wt% SDBS, the particle size of EMA core-(MMA/GMA) shell composite particles was high as $0.48{\mu}m$. We confirmed that 3 points of glass transition temperatures appear for multi core-shell composite particles compared to 1~2 points of glass transition temperatures appear for general copolymer particles. Overall, the adhesion strength of shell composite particles was in the order of EMA/MAA > EMA/2-HEMA > EMA/GMA.

• Proceedings of the KSME Conference
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• 2005.11a
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• pp.206.2-206.2
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• 2005

• Journal of KIISE
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• v.44 no.2
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• pp.115-123
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• 2017

A message processor is server software that receives non-realtime messages as well as realtime messages from clients that need to be processed within a deadline. With the recent advances of micro-processor technologies and Linux, the message processor is often implemented in Linux-based multi-core servers and it is important to use cores efficiently to maximize the performance of system in multi-core environments. Numerous research efforts on a real-time scheduler for the efficient utilization of the multi-core environments have been conducted. Typically, though, they have been conducted theoretically or via simulation, making a subsequent real-system application difficult. Moreover, many Linux-based real-time schedulers can only be used in a specific Linux version, or the Linux source code needs to be modified. This paper presents the design of a Linux-based message processor for multi-core environments that maps the threads to the cores at user level. The message processor is implemented through a modification of the traditional RM algorithm that consolidates the real-time messages into certain cores using a first-fit-based bin-packing algorithm; this minimizes the response-time delay of the non-real-time messages, while guaranteeing the violation rate of the real-time messages. To compare the performances, the message processor was implemented using the two multi-core-scheduling algorithms GSN-EDF and P-FP, which are provided by the LITMUS framework. The benchmarking results show that the response-time delay of non-real-time messages in the proposed system was improved up to a maximum of 17% to 18%.

• The KIPS Transactions:PartA
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• v.18A no.1
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• pp.1-10
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• 2011

Physical modeling has been widely used for sound synthesis since it synthesizes high quality sound which is similar to real-sound for musical instruments. However, physical modeling requires a lot of parameters to synthesize a large number of sounds simultaneously for the musical instrument, preventing its real-time processing. To solve this problem, this paper proposes a single instruction, multiple data (SIMD) based multi-core processor that supports real-time processing of sound synthesis of gayageum which is a representative Korean traditional musical instrument. The proposed SIMD-base multi-core processor consists of 12 processing elements (PE) to control 12 strings of gayageum in which each PE supports modeling of the corresponding string. The proposed SIMD-based multi-core processor can generate synthesized sounds of 12 strings simultaneously after receiving excitation signals and parameters of each string as an input. Experimental results using a sampling reate 44.1 kHz and 16 bits quantization show that synthesis sound using the proposed multi-core processor was very similar to the original sound. In addition, the proposed multi-core processor outperforms commercial processors(TI's TMS320C6416, ARM926EJ-S, ARM1020E) in terms of execution time ($5.6{\sim}11.4{\times}$ better) and energy efficiency (about $553{\sim}1,424{\times}$ better).

• Journal of IKEEE
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• v.16 no.4
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• pp.375-381
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• 2012

In this paper, we present an implementation of Viola-Jones algorithm in a multi-core SoC by using skin color information and a parallel processing method. In order to reduce unnecessary operations and improve the detection speed, we adopted a face detection algorithm based on skin color and deleted background image. The algorithm is functionally divided into several parts taking account of the size and the dependency so that the divided functions can be proceeded in parallel. Experiment results in SoC with built-in Cortex-A9 multi core show that it is about 1.8 times faster than the existing algorithm which is not divided.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.10
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• pp.2479-2496
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• 2013

Increasing demand for Full High-Definition (FHD) video and Ultra High-Definition (UHD) video services has led to active research on high speed video processing. Widespread deployment of multi-core systems has accelerated studies on high resolution video processing based on parallelization of multimedia software. Even if parallelization of a specific decoding step may improve decoding performance partially, such partial parallelization may not result in sufficient performance improvement. Particularly, entropy decoding has often been considered separately from other decoding steps since the entropy decoding step could not be parallelized easily. In this paper, we propose a parallelization technique called Integrated Multi-Threaded Parallelization (IMTP) which takes parallelization of the entropy decoding step, with other decoding steps, into consideration in an integrated fashion. We used the Simultaneous Multi-Threading (SMT) technique with appropriate thread scheduling techniques to achieve the best performance for the entire decoding step. The speedup of the proposed IMTP method is up to 3.35 times faster with respect to the entire decoding time over a conventional decoding technique for H.264/AVC videos.

• Design & Manufacturing
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• v.9 no.1
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• pp.9-13
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• 2015

The HEV/EV Traction Motor Core manufacturing technology is a core component of Traction Motor Core is a key technology for the manufacture of eco-friendly automotive industry is essential for the competitiveness of the country must obtain the technology. This study was performed to develop a Rotor Core of the HEV/EV Traction Motor using the first time in Korea multi-gate BMC injection molding technique. Executed by the experiment of this study are as follows. Study 1: Developed a multi-gate BMC injection mold for the magnet fixed to the Rotor Core. Study 2: Developed a production implementation and manufacturing technology of the Rotor Core. In this study, the develop products and manufacturing technologies implemented by the BMC injection mold development for Magnet fixed to the Rotor Core and the results are discussed.

• International Journal of Aeronautical and Space Sciences
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• v.5 no.2
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• pp.71-76
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• 2004

This paper describes the antenna analysis of the multi-beam for communicationsatellite. The design core parameters of the antenna system are optimal antennadiameter, feed horn type and hom size, F/D, and the coordinate of offset horns. Thepaper deals with the method to determine design core parameters of optimal antennadiameter, feed horn type and horn size. F/D, and the coordinate of offset horns, andthe performances of design result.