• The Transactions of the Korea Information Processing Society
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• v.13 no.3
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• pp.122-129
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• 2024

Though programming education has been stressed recently, the elementary, middle, and high school students are having trouble in programming education. Most programming environments for them are based on block coding, which hinders them from moving to text coding. The traditional PC environment has also troubles such as maintenance problems. In this situation, mobile applications can be considered as alternative programming environments. This paper addresses the design and implementation of coding applications for mobile devices. As a prototype, a Scheme interpreter mobile app is proposed, where Scheme is used for programming courses at MIT since it supports multi-paradigm programming. The implementation has the advantage of not consuming the network bandwidth since it is designed as a standalone application. According to the benchmark result, the execution time on Android devices, relative to that on a desktop, was 131% for the Derivative and 157% for the Tak. Further, the maximum execution times for the benchmark programs on the Android device were 19.8ms for the Derivative and 131.15ms for the Tak benchmark. This confirms that when selecting an Android device for programming education purposes, there are no significant constraints for training.

• Fire Science and Engineering
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• v.31 no.5
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• pp.53-62
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• 2017

Electric power which is the energy source of economy and industries requires long distance transportation due to regional difference between its production and consumption, and it is supplied through the multi-loop transmission and distribution system. Prior to its actual use, electric power flows through several transformations by voltage transformers in substations depending on the characteristics of each usage, and a transformer has the structure consisting of the main body, winding wire, insulating oil and bushings. A transformer fire that breaks out in substations entails the primary damage that interrupts the power supply to houses and commercial facilities and causes various safety accidents as well as the secondary economic losses. It is considered that causes of such fire include the leak of insulating oil resulting from the destruction of bottom part of bushings, and the chain reaction of fire due to insulating oil that reaches its ignition point within 1 second. The smoke detector and automatic fire extinguishing system are established in order to minimize fire damage, but a difficulty in securing golden time for extinguishing fire due to delay in the operation of detector and release of gas from the extinguishing system has become a problem. Accordingly, this study was carried out according to needs of active mechanism to prevent the spread of fire and block the leak of insulating oil, in accordance with the importance of securing golden time in extinguishing a fire in its early stage. A bushings fireproof structure was developed by applying the high temperature shape retention materials, which are expanded by flame, and mechanical flame cutoff devices. The bushings fireproof structure was installed on the transformer model produced by applying the actual standards of bushings and flange, and the full scale fire test was carried out. It was confirmed that the bushings fireproof structure operated at accurate position and height within 3 seconds from the flame initiation. It is considered that it could block the spread of flame effectively in the event of actual transformer fire.

• Restorative Dentistry and Endodontics
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• v.27 no.4
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• pp.421-431
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• 2002

C-shaped canal configuration is very difficult to treat because that clues about preoperative canal anatomy cannot be ascertained from clinical crown morphology and limited information can be derived from radiographic examination. This study was done to get more informations about the root and canal configuration of C-shape root by 3-dimensionally reconstructing for the purpose of enhancing success rate of endodontic treatment. 30 mandibular molars with C-shaped root were selected. Six photo images from occlusal, apical, mesial, distal, buccal, lingual directions and radiographic view were taken as preoperative ones to compare them with 3-D image. After crown reduction to the level of 1-2mm over pulpal floor was performed, teeth were stored in 5.25% sodium hypochlorite solution for the removal of pulp tissue and debris. They were cleaned under running water, allowed to bench dry and embedded in a self-curing resin. This resin block was serially ground with a microtome (Accutom-50, Struers, Denmark) and the image of each level was recorded by digital camera (FinePix S1-pro, Fuji Co., Japan). The thickness of each section was 0.25mm. Photographs of serial sections through all root canal were digitized using Adobe Photoshop 5.0 and then minimum thickness of open and closed sites were measured (open site is the surface containing occluso-apical groove closed site is oppsite). After dizitization using 3-D Doctor (Able software Corp, USA). 3D reconstruction of the outer surface of tooth and the inner surface of pulp space was made. Canal classsification of C-shaped roots was performed from this 3-D reconstructed image. The results were as follows : 1. Most C-shape rooted teeth showed lingual groove (28/30). 2 According to Vertuccis' calssification, type I, II, III, IV, VII were observed. but also new canal types suck as 2-3-2, 1-2-3-2. 2-3-2-1, 2-3-2-3 were shown. 3 There was little difference in minimum thickness on coronal and apical portions, but open site were thinner than closed site on mid portion. Conclusively, 3D reconstruction method could make the exact configurations of C-shape root possible to be visualized and analyzed from multi-directions. Data from minimum thickness recommend cleaning and shaping be more carefully done on dangerous mid portion.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.21 no.6
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• pp.225-229
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• 2011

Most of the silicon cutting methods using the multi-wire with the slurry injection have been used for wafers of the crystalline solar cell. But the productivity of slurry injection cutting type falls due to low cutting speeds. Also, the direct contact with the metal wire and silicon block increases the concentration of metallic impurities in the wafer's surface. In addition, the abrasive silicon carbide (SiC) generates pollutants. And production costs are rising because it does not re-use the worn wire. On the other hand, the productivity of the cutting method using the diamond coated wire is about 2 times faster than the slurry injection cutting type. Also, the continuous cutting using the used wire of low wear is possible. And this is a big advantage for reduced production costs. Therefore, the cutting method of the diamond coated wire is more efficient than the slurry injection cutting technique. In this study, each cutting type is analyzed using the surface characteristics of the solar wafer and will describe the effects of the manufacturing process of the solar cell. Finally, we will suggest improvement methods of the solar cell process for using the diamond cutting type wafer.

• The Journal of the Korea Contents Association
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• v.13 no.12
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• pp.38-47
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• 2013

An image coding based on MRC model, a kind of multi-layer image model, first segments a screen image into foreground, mask, and background layers, and then compresses each layer using a codec that is suitable to the layer. The mask layer defines the position of foreground regions such as textual and graphical contents. The colour signal of the foreground (background) region is saved in the foreground (background) layer. The mask layer which contains the segmentation result of foreground and background regions is of importance since its accuracy directly affects the overall coding performance of the codec. This paper proposes a new layer segmentation algorithm for the MRC based image coding. The proposed method extracts text pixels from the background using morphological top hat filtering. The application of white or black top hat transformation to local blocks is controlled by the information of relative brightness of text compared to the background. In the proposed method, the boundary information of text that is extracted from the edge map of the block is used for the robust decision on the relative brightness of text. Simulation results show that the proposed method is superior to the conventional methods.

• Journal of Korea Multimedia Society
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• v.3 no.5
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• pp.526-534
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• 2000

There have been many researches on the 3D graphic accelerator for high speed by needs of CAD/CAM,3D modeling, virtual reality or medical image. In this paper, an SIMD processor architecture for 3D graphic accelerator is proposed in order to improve the processing time of the 3D graphics, and a parallel Phong shading algorithm is presented to estimate performance of the proposed architecture. The proposed SIMD processor architecture for 3D graphic accelerator consists of PCI local bus interface, 16 Processing Elements (PE's), and Park's multi-access memory system (NAMS) that has 17 memory modules. A serial algorithm for Phong shading is modified for the architecture and the main key is to divide a polygon into $4\times{4}$ squares. And, for processing a square, 4 PE's are regarded as a PE Grou logically. Since MAMS can support block access type with interval 1, it is possible that 4 PE Groups process a square at a time. In consequence, 16 pixels are processed simultaneously. The proposed SIMD processor architecture is simulated by CADENCE Verilog-XL that is a package for the hardware simulation. With the same simulated results as that of the serial algorithm, the speed enhancement by the parallel algorithm to the serial one is 5.68.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.19-24
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• 2007

With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.40-49
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• 2008

A Frequency synthesizer for mobile-DTV applications is implemented using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors are chosen for VCO core to reduce phase noise. The measurement result of VCO frequency range is 800MHz-1.67GHz using switchable inductors, capacitors and varactors. We use varactor bias technique for the improvement of VCO gain linearity, and the number of varactor biasing are minimized as two. VCO gain deterioration is also improved by using the varactor switching technique. The VCO gain and interval of VCO gain are maintained as low and improved using the VCO frequency calibration block. The sigma-delta modulator for fractional divider is designed by the co-simualtion method for accuracy and efficiency improvement. The VCO, PFD, CP and LF are verified by Cadence Spectre, and the sigma-delta modulator is simulated using Matlab Simulink, ModelSim and HSPICE. The power consumption of the frequency synthesizer is 18mW, and the VCO has 52.1% tuning range according to the VCO maximum output frequency. The VCO phase noise is lower than -100dBc/Hz at 1MHz at 1MHz offset for 1GHz, 1.5GHz, and 2GHz output frequencies.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.503-510
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• 2006

Readout circuit is to convert signal occurred in a defector into suitable signal for image signal processing. In general, it has to possess functions of impedance matching with perception element, amplification, noise reduction and cell selection. It also should satisfies conditions of low-power, low-noise, linearity, uniformity, dynamic range, excellent frequency-response characteristic, and so on. The technical issues in developing image processing equipment for focal plane way (FPA) can be categorized as follow: First, ultraviolet (UV) my detector material and fine processing technology. Second, ReadOut IC (ROIC) design technology to process electric signal from detector. Last, package technology for hybrid bonding between detector and ROIC. ROIC enables intelligence and multi-function of image equipment. It is a core component for high value added commercialization ultimately. Especially, in development of high-resolution image equipment ROIC, it is necessary that high-integrated and low-power circuit design technology satisfied with design specifications such as detector characteristic, signal dynamic range, readout rate, noise characteristic, ceil pitch, power consumption and so on. In this paper, we implemented a $8\times8$ FPA prototype ROIC for reduction of period and cost. We tested unit block and overall functions of designed $8\times8$ FPA ROIC. Also, we manufactured ROIC control and image boards, and then were able to verify operation of ROIC by confirming detected image from PC's monitor through UART(Universal Asynchronous Receiver Transmitter) communication.