• Journal of Broadcast Engineering
• /
• v.1 no.2
• /
• pp.152-164
• /
• 1996

This paper describes the hardware architecture and implementation trade-offs of the Grand Alliance HDTV video encoder system. The implemented video encoder accepts video in 1125 line(30Hz) interlaced format, and produces a bit-stream compliant with the motion picture experts group version 2(MPEG-2) standards. The encoder processing includes large- area motion estimation and an advanced rate control mechanism. To keep the system complexity realizable, we adopt a fast hierarchical motion estimation method and developed its hardware architecture. Furthermore an adaptive perceptual quantization method is adopted to improve the perceptual quality. The developed system Is based on the 4-way parallel processing architecture and is implemented by using programmable IC, memory IC, and special-purpose processors such as DCT and motion estimation processors.

• Journal of Broadcast Engineering
• /
• v.2 no.1
• /
• pp.8-15
• /
• 1997

In this paper, a real-time operating Motion Picture Experts Group-1 (MPEG-1) audio encoder system is implemented using a TMS320C31 Digital Signal Processor (DSP) chip. The basic operation of the MPEG-1 audio encoder algorithm based on audio layer-2 and psychoacoustic model-1 is first verified by C-language. It is then realized using the Texas Instruments (Tl) assembly in order to reduce the overall execution time. Finally, the actual BSP circuit board for the encoder system is designed and implemented. In the system, the side-modules such as the analog-to-digital converter (ADC) control, the input/output (I/O) control, the bit-stream transmission from the DSP board to the PC and so on, are utilized with a field programmable gate array (FPGA) using very high speed hardware description language (VHDL) codes. The complete encoder system is able to process the stereo audio signal in real-time at the sampling frequency 48 kHz, and produces the encoded bit-stream with the bit-rate 192 kbps. The real-time operation capability of the encoder system and the good quality of the decoded sound are also confirmed using various types of actual stereo audio signals.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.40 no.5
• /
• pp.417-425
• /
• 2003

H.264, which is the latest video coding standard of both ITU-T(International Telecommunication Union-Telecommunication standardization sector) and MPEG(Moving Picture Experts Group), adopts new video coding tools such as variable block size motion estimation, multiple reference frames, quarter-pel motion estimation/compensation(ME/MC), 4${\times}$4 Integer DCT(Discrete Cosine Transform), and Rate-Distortion Optimization, etc. These new video coding tools provide good coding of efficiency compared with existing video coding standards as H.263, MPEG-4, etc. However, these new coding tools require the increase of encoder complexity. Therefore, in order to apply H.264 to many real applications, fast algorithms are required for H.264 coding tools. In this paper, when encoder MacroBlock(MB) mode is decided by rate-distortion optimization tool, fast mode decision algorithm by skipping variable block size ME/MC and spatial-predictive coding, which occupies most encoder complexity, is proposed. In terms of computational complexity, the proposed method runs about 4 times as far as JM(Joint Model) 42 encoder of H.264, while the PSNR(peak signal-to-noise ratio)s of the decoded images are maintained.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.2
• /
• pp.352-358
• /
• 2004

This paper is studied the improvement of performance for moving picture encoder using H.263. This is used the new motion vector search algorithm using a relation with neighborhood search point and is applied the integer DCT for the encoder. The integer DCT behaves DCT by the addition operation of the integer using WHT and a integer lifting than conventional DCT that needs the multiplication operation of a floating point number. Therefore, the integer Dn can reduce the operation amount than basis DCT with having an equal PSNR. The new motion vector search algorithm is showed almost similar PSNR as reducing the operation amount than the conventional motion vector search algorithm. To experiment a compatibility of the integer DCT and the conventional DCT, according to result compare case that uses a method only and case that uses the alternate two methods of the integer DCT or the conventional DCT to H.263 encoder and decoder, case that uses the alternate two methods is showed doing not deteriorate PSNR-and being each other compatible visually than case that uses an equal method only.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2009.01a
• /
• pp.618-622
• /
• 2009

An improvement of standard encoder has been saturated recently. However, new coding method does not have a compatibility with conventional standard. To solve this problem, new concept coding method that has a semicompatibility with standard may be discussed. On the other hand, cyclic Intra-picture coding is used for access and refreshment. However, I-picture spend large amount of bits. An enhancement of I-picture is desired with keeping its refreshment performance. Further, it's a problem that quality change at the border of GOP because of its independency. To respond these, we propose the coding which is applied an inter-frame processing at the border of GOP. Applied method is the reduction of quantization error using the motion compensated inter-picture processing. In this report, we check the improvement of the efficiency and the compatibility of proposed method. As a result of examination, we recognize that the total gain is maximally 1.2dB in PSNR. Generally, the degradation of performance in standard decoding is smaller than its gain. Also the refreshment performance is tested.

• Journal of Broadcast Engineering
• /
• v.17 no.1
• /
• pp.140-151
• /
• 2012

In Wyner-Ziv coding, key picture is encoded by conventional H.264/AVC intra coding which has low complexity. Although inter coding is more efficient than intra coding, its complexity is much higher than intra coding due to its motion estimation. Since the main feature of Wyner-Ziv coding is low complexity of encoder, inter coding is not suitable to encode key picture in Wyner-Ziv coding. However, inter picture coding with zero motion vector can be usable for Wyner-Ziv key picture coding instead of intra coding. Moreover, while current transform-domain Wyner-Ziv residual coding only utilizes temporal correlation of WZ picture, if zero motion coding is jointly used to encode key picture in transform-domain Wyner-Ziv residual coding, there will be a significant improvement in R-D performance. Experimental results show that the complexity of Wyner-Ziv coding with the proposed zero motion key picture coding is higher than conventional Wyner-Ziv coding with intra key picture coding by about 9%, however, there are BDBR gains up to 54%. Additionally, if the proposed zero motion key coding is implemented on top of the transform-domain Wyner-Ziv residual coding, the result shows rate gains up to 70% in BDBR compared to conventional Wyner-Ziv coding with intra key picture coding.

• Proceedings of the IEEK Conference
• /
• 2003.07e
• /
• pp.2072-2075
• /
• 2003

This paper is studied the high speed processing moving picture encodec to compress and encode a moving picture by real time. This is used the new motion vector search algorithm with smallest search point in H.263 encodec, and is applied the integer DCT for the encodec by converting a moving picture. The integer DCT behaves DCT by the addition operation of the integer using WHT and a integer lifting than conventional DCT that needs the multiplication operation of a floating point number. Therefore, the integer DCT can reduce the operation amount than basis DCT with having an equal PSNR because the multiplication operation of a floating point number does not need.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.3
• /
• pp.594-600
• /
• 2017

This paper proposes a global search based motion estimation algorithm for high performance HEVC encoder and its hardware architecture. To eliminate temporal redundancy, motion estimation in HEVC inter-view prediction uses global search and fast search algorithm to search for a predicted block having a high correlation with the current PU in an interpolated reference picture. The global search method predicts the motion of all candidate blocks in a given search area, thus ensuring optimal results, but has a disadvantage of large computation time. Therefore we propose a new algorithm that reduces computational complexity by reusing SAD operation in global search to reduce computation time of inter prediction. As a result of applying the proposed algorithm to standard software HM16.12, the computation time was reduced by 61%, BDBitrate by 11.81%, and BDPSNR by about 0.5% compared with the existing search algorithm. As a result of hardware design, the maximum operating frequency is 255 MHz and the total number of gates is 65.1K.

• The Journal of the Korea Contents Association
• /
• v.8 no.5
• /
• pp.72-81
• /
• 2008

High Performance DSP usually supports cache and internal memory. For an optimal implementation of a multimedia stream application on such a high performance DSP, one needs to utilize the cache and internal memory efficiently. In this paper, we investigate performance analysis of cache, and internal memory configuration and placement necessary to achieve an optimal implementation of multimedia stream applications like motion picture encoder on high performance DSP, TMS320C6000 series, and propose strategies to improve performance for cache and internal memory placement. From the results of analysis and experiments, it is verified that 2-way L2 cache configuration with the remaining memory configured as internal memory shows relatively good performance. Also, it is shown that L1P cache hit rate is enhanced when frequently called routines and routines having caller-callee relationships with them are continuously placed in the internal memory and that L1D cache hit rate is enhanced by the simple change of the data size. The results in the paper are expected to contribute to the optimal implementation of multimedia stream applications on high performance DSPs.

• The Journal of the Korea Contents Association
• /
• v.7 no.12
• /
• pp.262-272
• /
• 2007

SAD (Sum of Absolute Difference) algorithm is the most frequently executing routine in motion estimation, which is the most demanding process in motion picture encoding. To enhance the performance of motion picture encoding on a VLIW processor, an optimal implementation of SAD algorithm on VLIW processor should be accomplished. In this paper, we propose an implementation of optimal scheduling of SAD algorithm with conditional branch on a VLIW-based high performance DSP. We first transform the nested loop with conditional branch of SAD algorithm into a single loop with conditional branch which has a large enough loop body to utilize fully the ILP capability of VLIW DSP and has a conditional branch to make the escape from loop to be achieved as soon as possible. And then we apply a modulo scheduling technique to the transformed single loop. We test the proposed implementation on TMS320C6713, and analyze the code size and performance with respect to processing time. Through experiments, it is shown that the SAD implementation proposed in this paper has small code size appropriate for embedded applications, and the H.263 encoder with the proposed SAD implementation performs better than other H.263 encoder with other SAD implementations.