• 대한전자공학회논문지SD
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• 제41권4호
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• pp.57-66
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• 2004

본 논문에서는 RNS(residue number systems) 몽고메리 모듈라 곱셈기 기반의 2,048 비트 RSA 설계를 제안한다. RNS는 긴 워드에 대한 모듈라 연산을 짧은 워드로 분할하여 고속 병렬 모듈라 연산을 처리하는 시스템으로써 본 논문에서는 RNS 몽고메리 모듈라 곱셈 연산을 위해 Wallace 트리 모듈라 곱셈기 기반의 Montgomery reduction method(MRM)［1］와 33개의 64 비트 RNS base 를 도입하였다. 또한, 고속 RNS 모듈라 곱셈 연산을 위해 Chinese remainder theorem(CRT)［2］기반의 개선된 base extension 알고리즘을 제안한다. 본 논문에서 제시한 RNS 기반의 2,048 비트 RSA는 삼성 0.35㎛ 공정을 사용하여 기능을 검증하였으며 100㎒에서 2.53㎳ 연산 속도 결과를 얻었다.

• Journal of information and communication convergence engineering
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• 제15권4호
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• pp.212-216
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• 2017

In this paper, we introduce novel techniques to improve the high performance of AE functions on modern high-end IoT platforms (ARM-NEON), which support SIMD and cryptography instruction sets. For the Sophie Germain Counter Mode of operation (SGCM), counter modes of encryption and prime field multiplication are required. We chose the Montgomery multiplication for modular multiplication. We perform Montgomery multiplication in a parallel way by exploiting both the ARM and NEON instruction sets. Specifically, the NEON instruction performed 128-bit integer multiplication and the ARM instruction performed Montgomery reduction, simultaneously. This approach hides the latency for ARM in the NEON instruction set. For a high-speed counter mode of encryptions for both AE functions, we introduced two-level computations. When the tasks were large volume, we switched to the NEON instruction to execute the encryption operations. Otherwise, we performed the encryptions on the ARM module.

• International Journal of Internet, Broadcasting and Communication
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• 제16권1호
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• pp.17-28
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• 2024

As listed as one of the most important requirements for Post-Quantum Cryptography standardization process by National Institute of Standards and Technology, the resistance to various side-channel attacks is considered very critical in deploying cryptosystems in practice. In fact, cryptosystems can easily be broken by side-channel attacks, even though they are considered to be secure in the mathematical point of view. The timing attack(TA) and the simple power analysis attack(SPA) are such side-channel attack methods which can reveal sensitive information by analyzing the timing behavior or the power consumption pattern of cryptographic operations. Thus, appropriate measures against such attacks must carefully be considered in the early stage of cryptosystem's implementation process. The Montgomery multiplier is a commonly used and classical gadget in implementing big-number-based cryptosystems including RSA and ECC. And, as recently proposed as an alternative of building blocks for implementing post quantum cryptography such as lattice-based cryptography, the big-number multiplier including the Montgomery multiplier still plays a role in modern cryptography. However, in spite of its effectiveness and wide-adoption, the multiplier is known to be vulnerable to TA and SPA. And this paper proposes a new countermeasure for the Montgomery multiplier against TA and SPA. Briefly speaking, the new measure first represents a multiplication operand without 0 digits, so the resulting multiplication operation behaves in a very regular manner. Also, the new algorithm removes the extra final reduction (which is intrinsic to the modular multiplication) to make the resulting multiplier more timing-independent. Consequently, the resulting multiplier operates in constant time so that it totally removes any TA and SPA vulnerabilities. Since the proposed method can process multi bits at a time, implementers can also trade-off the performance with the resource usage to get desirable implementation characteristics.

• 정보보호학회논문지
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• 제33권2호
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• pp.243-252
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• 2023

NIST PQC 표준화 작업 Round 4에 올라 있던 유일한 아이소제니 기반 KEM 알고리즘인SIKE에대한효율적인 키 복구 공격이 발표됨에 따라, 이를 대체할 수 있는 키 교환 알고리즘인 CSIDH가 다시주목받고 있다. CSIDH는 현재까지 알려진 공격에 안전한 아이소제니 기반 키 교환 알고리즘으로, CRS 스킴을 현대화하여 효율적인 NIKE를 제공한다. 본 논문에서는 CSIDH-512를 ARM Cortex-M7에서 구현하고 three-level 하이브리드 몽고메리 감산을 적용하여 최적화한 성능을 측정한 뒤 그 결과 및 한계에 대해 서술하고 향후 연구방향을 제시한다. 이는 기존에 제시되지 않았던 32-bit 임베디드 기기에서의 CSIDH 구현으로, 향후 다양한 임베디드 환경에서CSIDH 및 파생 암호 알고리즘을 구현하는데 본 논문의 결과를 이용할 수 있을 것으로 기대한다.

• 한국통신학회논문지
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• 제23권4호
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• pp.1024-1034
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• 1998

정보통신망에서 사용하는 공개키 암호시스템은 대부분 지수 연산을 사용한다. 하지만, 암호시스템은 안전성을 고려한 큰 수의 지수 연산을 사용하기 때문에 많은 계산 량과 준비시간을 요구한다. 이러한 문제점을 해결하기 위하여 모듈러 감소 연산에서 Montgomery, Yang, Kawamura 등이 사전계산 방법, 중간계산, 그리고 테이블을 사용하는 방법을 제안하였으며, 지수 연산에서 Coster, Brickel, Lee 등이 addition chain, window, 그리고 고정된 수를 사용하는 경우 사전 계산을 하는 방법을 제안하였다. 본 논문에서는 sparse 소수를 사용한 모듈러 감소 연산 방법을 제안하고 지수연산시 계산 량을 줄이는 방법을 제안한다. 이는 이산대수 방식의 암호시스템에서 매우 효과적으로 적용할 수 있다.

• 디지털산업정보학회논문지
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• 제18권1호
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• pp.1-9
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• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.

• 한국정보통신학회논문지
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• 제24권6호
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• pp.736-743
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• 2020

모듈러 곱셈은 타원곡선 암호 (elliptic curve cryptography; ECC), RSA 등의 공개키 암호에서 중요하게 사용되는 산술연산 중 하나이며, 모듈러 곱셈기의 성능은 공개키 암호 하드웨어의 성능에 큰 영향을 미치는 핵심 요소가 된다. 본 논문에서는 워드기반 몽고메리 모듈러 곱셈 알고리듬의 효율적인 하드웨어 구현에 대해 기술한다. 본 논문의 모듈러 곱셈기는 SEC2 ECC 표준에 정의된 소수체 GF(p)와 이진체 GF(2k) 상의 11가지 필드 크기를 지원하여 타원곡선 암호 프로세서의 경량 하드웨어 구현에 적합하도록 설계되었다. 제안된 곱셈기 구조는 부분곱 생성 및 가산 연산과 모듈러 축약 연산이 파이프라인 방식으로 처리하며, 곱셈 연산에 소요되는 클록 사이클 수를 약 50% 줄였다. 설계된 모듈러 곱셈기를 FPGA 디바이스에 구현하여 하드웨어 동작을 검증하였으며, 65-nm CMOS 표준셀로 합성한 결과 33,635개의 등가 게이트로 구현되었고, 최대 동작 클록 주파수는 147 MHz로 추정되었다.

• ETRI Journal
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• 제41권6호
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• pp.863-872
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• 2019

Elliptic curve cryptography is a relatively lightweight public-key cryptography method for key generation and digital signature verification. Some lightweight curves (eg, Curve25519 and Curve Ed448) have been adopted by upcoming Transport Layer Security 1.3 (TLS 1.3) to replace the standardized NIST curves. However, the efficient implementation of Curve Ed448 on Internet of Things (IoT) devices remains underexplored. This study is focused on the optimization of the Curve Ed448 implementation on low-end IoT processors (ie, 8-bit AVR and 16-bit MSP processors). In particular, the three-level and two-level subtractive Karatsuba algorithms are adopted for multi-precision multiplication on AVR and MSP processors, respectively, and two-level Karatsuba routines are employed for multi-precision squaring. For modular reduction and finite field inversion, fast reduction and Fermat-based inversion operations are used to mitigate side-channel vulnerabilities. The scalar multiplication operation using the Montgomery ladder algorithm requires only 103 and 73 M clock cycles on AVR and MSP processors.

• 디지털산업정보학회논문지
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• 제16권2호
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• 생물정신의학
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• 제4권1호
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• pp.116-120
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• 1997

This study investigated the antidepressant efficacy and it's impact on the quality of life of depressed patients. We performed Hamilton Depression Rating Scale(HDRS), and Montgomery-Asberg Depression Rating Scale(MADRS), and Health-related Quality of Life Questionnaire(HQLQ) to both tricyclic antidepressant(TCA) and sertraline groups. There were 16 subjects in this study. The tricyclic group had 9 subjects and the sertraline group had 7. The TCA and sertraline produced a similar degree of response. Both groups experienced a reduction of 70% or more in mean HDRS and MADRS total score after 6wks. In HQLQ, the TCAs group also showed improved bed disability days, alertness behavior, and social interaction, the sertraline group showed improved health perception, alertness behavior, home management, and social interaction. We suggested that the improvement of "Quality of life" were not in proportion to the clinical symptom's improvement. Therefore, clinicians should consider the benefit of antidepressant treatment in terms of quality of life.