• 전력전자학회논문지
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• 제25권1호
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• pp.61-67
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• 2020

This study deals with the modulation index (MI) of a voltage source converter (VSC) HVDC system based on a modular multilevel converter (MMC). In the two-level converter, the purpose of the MI is to maximize the achievable AC voltage of the converter from a fixed DC voltage. Unlike that in a two-level converter, the MI in the MMC topology plays a role in making the converter a voltage source using a capacitor. The circulating current in the MMC distorts the AC voltage reference, and the distortion affects the MI. In addition, the AC network conditions, such as AC voltage variation and reactive power, affect the MI. Therefore, the MI should be optimized with consideration of internal and external factors. This study proposes a method to optimize the MI of an MMC HVDC system.

• 전력전자학회논문지
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• 제22권4호
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• pp.285-296
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• 2017

This paper proposes an improved modulation scheme for the medium voltage modular multi-level converter (MMC), which operates in the nearest level control and applies in the medium voltage direct current (MVDC) system. In the proposed modulation scheme, the offset (neutral-to-zero output) voltage is adjusted, with the phase voltage magnitude, thereby maintaining a constant value with N+1 level in the controllable modulation index (MI) range. In order to confirm the proposed scheme's validity, computer simulations for the 22.9 kV - 25 MVA MMC were performed with PSCAD/EMTDC, as well as hardware experiments for the 380 V - 10 kVA MMC. The proposed modulation scheme offers to build a constant pole voltage regardless of the MI value, and to build a phase voltage with improved total harmonic distortion (THD).

• 전력전자학회논문지
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• 제13권1호
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• pp.22-32
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• 2008

본 논문에서는 전철 구동용 견인 전동기의 구동을 위한 과변조 영역에서의 NPC형 3-레벨 인버터의 출력전압 선형화 기법을 제안한다. 과변조 영역은 Modulation Index: MI에 따라서 2가지 모드로 나누었으며 과변조영역 I에서는 퓨리에 시리즈를 통한 기본파성분의 크기로 유도된 reference angle을 사용하였다. 과변조영역 II에서는 과변조영역 I과 같은 방법으로 holding angle을 구하여 사용하였다. 이 두 가지 과변조기법을 통하여 PWM 인버터 출력전압을 1펄스 모드까지 선형적으로 획득할 수 있다.

• Journal of Power Electronics
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• 제18권4호
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• pp.1037-1050
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• 2018

This paper presents a novel reconfigurable selective harmonic elimination technique to control harmonics over a wide range of Modulation Indexes (MI) in Multi-Level Inverter (MLI). In the proposed method, the region of the MI is divided into various sectors and expressions are formulated with different switching patterns for each of the sectors. A memetic BBO-MAS (Biogeography Based Optimization - Mesh Adaptive direct Search) optimization algorithm is proposed for solving the Selective Harmonic Elimination - Pulse Width Modulation (SHE-PWM) technique. An experimental prototype is developed using a Field Programmable Gate Array (FPGA) and their FFT spectrums are analyzed over a wide range of MI using a fluke power logger. Simulation and experimental results have validated the performance of the proposed optimization algorithms and the reconfigurable SHE-PWM technique. Further, the sensitivity of the harmonics has been analyzed considering non-integer variations in the magnitude of the input DC sources.

• Journal of Power Electronics
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• 제9권3호
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• pp.481-490
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• 2009

This paper describes a SVPWM overmodulation scheme of NPC type three-level inverter for traction drives which extends the modulation index from MI=0.907 to unity. SVPWM strategy is organized by two operation modes of under-modulation and over-modulation. The switching states under the under-modulation modes are determined by dividing them with two linear regions and one hybrid region the same as the conventional three-level inverter. On the other hand, under the over-modulation mode, they are generated by doing it with two over-modulation regions the same as the conventional over-modulation strategy of a two level inverter. Following the description of over-modulation scheme of a three-level inverter, the system description of a vector controlled induction motor for traction drives has been discussed. Finally, the validity of the proposed modulation algorithm has been verified through simulation and experimental results.

• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.2168-2180
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• 2014

In this paper, a generalized power loss algorithm for multilevel neutral-point clamped (NPC) PWM inverters is presented, which is applicable to any level number of multilevel inverters. In the case of three-level inverters, the conduction loss depends on the MI (modulation index) and the PF (power factor), and the switching loss depends on a switching frequency, turn-on and turn-off energy. However, in the higher level of inverters than the three-level, the loss of semiconductor devices cannot be analyzed by conventional methods. The modulation depth should be considered in addition, to find the different conducting devices depending on the MI. In a case study, the power loss analysis for the three- and five-level NPC inverters has been performed with the proposed algorithm. The validity of the proposed algorithm is verified by simulation for the three-and five-level NPC inverters and experiment for three-level NPC inverter.

• Journal of Power Electronics
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• 제14권1호
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• pp.48-60
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• 2014

Multilevel inverters have been widely used for high-voltage and high-power applications. Their performance is greatly superior to that of conventional two-level inverters due to their reduced total harmonic distortion (THD), lower switch ratings, lower electromagnetic interference, and higher dc link voltages. However, they have some disadvantages such as an increased number of components, a complex pulse width modulation control method, and a voltage-balancing problem. In this paper, a novel nine-level reduced switch cascaded multilevel inverter based on a multilevel DC link (MLDCL) inverter topology with reduced switching components is proposed to improve the multilevel inverter performance by compensating the above mentioned disadvantages. This topology requires fewer components when compared to diode clamped, flying capacitor and cascaded inverters and it requires fewer carrier signals and gate drives. Therefore, the overall cost and circuit complexity are greatly reduced. This paper presents modulation methods by a novel reference and multicarrier based PWM schemes for reduced switch cascaded multilevel inverters (RSCMLI). It also compares the performance of the proposed scheme with that of conventional cascaded multilevel inverters (CCMLI). Simulation results from MATLAB/SIMULINK are presented to verify the performance of the nine-level RSCMLI. Finally, a prototype of the nine-level RSCMLI topology is built and tested to show the performance of the inverter through experimental results.

• Journal of Power Electronics
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• 제13권1호
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• pp.113-121
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• 2013

This paper introduces a simple core loss calculation method for output filter inductor in pulse width modulation (PWM) DC-AC inverter. Amorphous C-core (AMCC-320) is used to analyze the core loss. In order to measure core loss of the output filter inductor and validate the proposed method, a single-phase half-bridge inverter and a calorimeter are used. By changing switching frequency and modulation index (MI) of the inverter, core loss of the AMCC-320 is measured with the lab-made calorimeter and the results are compared with calculated core loss. The proposed method can be easily extended to other core loss calculation of various converters.

• 전력전자학회논문지
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• 제19권2호
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• pp.173-183
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• 2014

In this paper, an analysis of power losses for the three-level T-type and neutral-point clamped (NPC) PWM inverters is presented, in which the conduction and switching losses of semiconductor devices of the inverters are taken into account. In the inverter operation, the conduction loss depends on the modulation index (MI) and power factor (PF), whereas the switching loss depends on the switching frequency. Power losses for the T-type and NPC inverters are analyzed and calculated at the different operating points of MI, PF and the switching frequency, in which the four different models of semiconductor devices are adopted. In the case of lower MI, the NPC-type is more efficient than the T-type, and vice versa. The validity of the power loss analysis has been verified by the simulation results.

• Journal of Power Electronics
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• 제19권6호
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• pp.1496-1504
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• 2019

This paper proposes a new THD reduction algorithm for modular multilevel converters (MMCs) with offset voltage injection operated in nearest level modulation (NLM). High voltage direct current (HVDC) is actively introduced to the grid connection of offshore wind powers, and this paper deals with a voltage generation technique with an MMC for wind power generation. In the proposed method, third harmonic voltage is added for reducing the THD. The third harmonic voltage is adjusted so that each of the pole voltage magnitudes maintains a constant value with a maximum number of (N+1) levels, where N is the number of sub-modules per arm. By using the proposed method, the THD of the output voltage is mitigated without increasing the switching frequency. In addition, the proposed method has advantageous characteristics such as simple implementation. As a part of this study, this paper compares the THD results of the conventional method and the proposed method with offset voltage injection to reduce the THD. In this paper, simulations have been carried out to verify the effectiveness of the proposed scheme, and the proposed method is implemented by a HILS (Hardware in the Loop Simulation) system. The obtained results show agreement with the simulation results. It is confirmed that the new scheme achieved the maximum level output voltage and improved the THD quality.