• Journal of Wellbeing Management and Applied Psychology
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• v.7 no.3
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• pp.67-72
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• 2024

This study developed a dry composite module-type deodorization facility with Twisting airflow changes and two forms (catalyst, adsorbent) within one module. Experiments were conducted to evaluate the reduction efficiency of odor substances C₈H₇N and C₉H₉N. The device combines UV oxidation using TiO₂, catalytic oxidation using MnO₂, and adsorption using A/C in five different methods. Data analysis of experimental results utilized the statistical package program Python 3.12. The program applied frequency analysis of odor removal efficiency, one-way ANOVA, and post-hoc tests, with statistical significance determined by p-value to ensure reliability and validity of the measurements. Results indicated that the highest removal efficiency of C₈H₇N and C₉H₉N was achieved by the UV+A/C method, suggesting the superior effectiveness and efficiency of the developed device. Combining multiple processes and technologies within one module enhanced odor treatment efficiency compared to using a single method. The device's modularity allows for flexibility in adapting to various sewage treatment scenarios, offering easy maintenance and cost-effective deodorization. This composite reaction module device can apply multiple technologies, such as biofilters, plasma, activated carbon filters, UV-photocatalysis, and electromagnetic-chemical systems. However, this study focused on UV-photocatalysis, catalysts, and activated carbon filters. Ultimately, the research demonstrates the practical applicability of this innovative device in real sewage treatment operations, showing excellent reduction efficiency and effectiveness by integrating UV oxidation, TiO₂ photocatalysis, MnO₂ catalytic oxidation, and A/C adsorption within a modular system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.3
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• pp.419-426
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• 2021

A high-performance elliptic curve cryptography processor (HP-ECCP) was designed to support five field sizes of 192, 224, 256, 384 and 521 bits over GF(p) defined in NIST FIPS 186-2, and it provides eight modes of arithmetic operations including ECPSM, ECPA, ECPD, MA, MS, MM, MI and MD. In order to make the HP-ECCP resistant to side-channel attacks, a modified left-to-right binary algorithm was used, in which point addition and point doubling operations are uniformly performed regardless of the Hamming weight of private key used for ECPSM. In addition, Karatsuba-Ofman multiplication algorithm (KOMA), Lazy reduction and Nikhilam division algorithms were adopted for designing high-performance modular multiplier that is the core arithmetic block for elliptic curve point operations. The HP-ECCP synthesized using a 180-nm CMOS cell library occupied 620,846 gate equivalents with a clock frequency of 67 MHz, and it was evaluated that an ECPSM with a field size of 256 bits can be computed 2,200 times per second.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.10
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• pp.2497-2513
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• 2013

In 2010, Dijk et al. demonstrated a simple somewhat homomorphic encryption (HE) scheme over the integers of which this simplicity came at the cost of a public key size in $\tilde{O}({\lambda}^{10})$. Although in 2011 Coron et al. reduced the public key size to $\tilde{O}({\lambda}^7)$, it is still too large for practical applications, especially for the cloud computing. In this paper, we propose a new form of somewhat HE scheme to reduce further the public key size and a variation of the scheme to optimize the ciphertext size. First of all, we propose a new somewhat HE scheme which is built on the hardness of the approximate greatest common divisor (GCD) problem of two integers, where the public key size in the scheme is reduced to $\tilde{O}({\lambda}^3)$. Furthermore, we can reduce the length of the ciphertext of the new somewhat HE scheme by applying the modular reduction technique. Additionally, we give simulation results for evaluating ability of the proposed scheme.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.145-151
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• 2003

This study focuses on the hardware implementation of fast and low-complexity multiplier over GF(2$^{m}$ ). Finite field multiplication can be realized in two steps: polynomial multiplication and modular reduction using the irreducible polynomial and we will treat both operation, separately. Polynomial multiplicative operation in this Paper is based on the Permestzi's algorithm, and irreducible polynomial is defined AOP. The realization of the proposed GF(2$^{m}$ ) multipleker-based multiplier scheme is compared to existing multiplier designs in terms of circuit complexity and operation delay time. Proposed multiplier obtained have low circuit complexity and delay time, and the interconnections of the circuit are regular, well-suited for VLSI realization.

• Journal of Power Electronics
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• v.17 no.2
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• pp.411-421
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• 2017

An approach based on a 2D lumped model is presented to quantify the voltage transfer gain (VTG) in power converter low power planes. The advantage of the modeling approach is the ease with which typical noise reduction devices such as decoupling capacitors or ferrite beads can be integrated into the model. This feature is enforced by a new modular approach based on effective matrix partitioning, which is presented in the paper. This partitioning is used to decouple power plane equations from external device impedance, which avoids the need for rewriting of a whole set of equation at every change. The model is quickly solved in the frequency domain, which is well suited for an automated layout optimization algorithm. Using frequency domain modeling also allows the integration of frequency-dependent devices such inductors and capacitors, which are required for realistic computation results. In order to check the precision of the modeling approach, VTGs for several layout configurations are computed and compared with experimental measurements based on scattering parameters.

• Korean Journal of Construction Engineering and Management
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• v.16 no.4
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• pp.129-138
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• 2015

In this study, the road construction field of high impact in the construction industry were selected, and the analysis of the detailed technology level was carried out. and we derived the main fields for future overseas. As results, the technology level of road facilities in korea was high about road operations and management sector, while it was relatively row about road pavements. And this study, we analyzed the economic, social and technological priority, and derived main fields to have the high investment efficiency. A derived items are found to be "maintenance-free Modular Road Pavements" and "Cities temperature reduction-type road".

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.8
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• pp.1046-1054
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• 2014

In this paper, a hardware prototype for the 10kVA 11-level MMC was built and various experimental works were conducted to verify the operation algorithms of MMC. The hardware prototype was designed using computer simulation with PSCAD/EMTDC software. After manufactured in the lab, the hardware prototype was tested to verify the modulation algorithms to form the output voltage, the balancing algorithm to equalize the sub-module capacitor voltage, and the redundancy operation algorithm to improve the system reliability. The developed hardware prototype can be utilized for analyzing the basic operation and performance improvement of MMC according to the modulation and redundancy operation scheme. It also can be utilize to analyze the basic operational characteristics of HVDC system based on MMC.

• Journal of the Korean Society of Safety
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• v.27 no.1
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• pp.26-31
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• 2012

Wood-plastic composites represents a growing class of materials used by the residential construction industry and furniture industry. In this study, the effect of flame retardants on the flammability and mechanical properties of wood flour-high density polyethylene(HDPE) composites were studied. we were manufactured wood flour-HDPE composites by modular intermeshing co-rotating twin screw extruder with L/D ratio of 42. The flame retardant properties were used limiting oxygen index(LOI) and mechanical properties were measured by universal testing machine(UTM). The Morphological analysis of composites were analyzed by Scanning electron microscope(SEM). It was found that Ammonium polyphosphate can effectively reduce the flammability of the wood flour-HDPE composites. Marginal reduction in the mechanical properties of the composites was found with addition of flame retardants. SEM images showed that the coupling agent improved wood flour-HDPE interfacial bonding.

• Journal of Power Electronics
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• v.18 no.2
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• pp.502-510
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• 2018

A circulating current is a major problem caused by directly connecting voltage-source inverters (VSIs) in parallel. This circulating current occurs as a zero-sequence current between the inverters by specific switch states. Several studies have presented alternatives using hardware and software methods. When coupled inductors (CIs) are employed for the high-frequency circulating current, a controller is required to prevent the low-frequency circulating current from saturating the CIs. In this study, the zero-sequence circulating current and its alternatives are investigated using hardware and mathematical description. A high-performance circulating current controller is proposed by applying a repetitive controller to the zero-sequence current control loop. The proposed controller can effectively minimize the low-frequency circulating current without any data sharing between the inverters in unfavorable conditions. It can also be applicable to the modular configuration of parallel three-phase VSIs. Experimental results verify the performance of the proposed controller.

• Journal of the Korea Society of Computer and Information
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• v.15 no.11
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• pp.157-162
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• 2010

Due to the IT development, RFID/USN became very familiar means of communication. However, because of increased number, security, and size constraints of nodes, it is insufficient to implement a variety of services. To solve these problems, this paper suggests RI-RSA, which is an appropriate asymmetric cryptographic system for RFID/USN environment. The proposed RI-RSA cryptographic system is easy to implement. To increase the processing speed, RI-RSA was suggested by subdividing the multiplication section into two-dimensional, where bottleneck phenomena occurs, and it was implemented in the hardware chip level. The simulation result verified that it caused 6% of circuit reduction, and for the processing speed, RI-RSA was 30% faster compare to the existing RSA.