• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.8
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• pp.1075-1081
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• 2010

Recently, the results of many studies have clarified the successful performance of magnetostrictive transducers in which a ferromagnetic patch is used for the transduction of guided shear waves; this is because a thin ferromagnetic patch with strong magnetostriction is very useful for generating and detecting shear wave. This investigation deals with bulk shear wave transduction by means of magnetostriction; on the other hand, the existing studies have been focused on guided shear waves. A modular transducer was developed; this transducer comprised a coil, magnets, and a thin ferromagnetic patch that was made of Fe-Co alloy. Some experiments were conducted to verify the performance of the developed transducer. Radiation directivity pattern of the developed transducer was obtained, and a test to detect the damage on a side drill hole of a steel block specimen was carried out. From the results of these tests, the good performance of the transducer for nondestructive testing was verified on the basis of the signal-to-noise ratio and narrow beam directivity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.7
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• pp.1071-1077
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• 2022

A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.