• Journal of information and communication convergence engineering
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• v.11 no.1
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• pp.50-55
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• 2013

In this paper, we propose a parallel intra-operation unit and a memory architecture for improving the performance of intra-prediction, which utilizes spatial correlation in an image to predict the blocks and contains 17 prediction modes in total. The design is targeted for portable devices applying H.264/AVC decoders. For boosting the performance of the proposed design, we adopt a parallel intra-operation unit that can achieve the prediction of 16 neighboring pixels at the same time. In the best case, it can achieve the computation of one luma $16{\times}16$ block within 16 cycles. For one luma $4{\times}4$ block, a mere one cycle is needed to finish the process of computation. Compared with the previous designs, the average cycle reduction rate is 78.01%, and the gate count is slightly reduced. The design is synthesized with the MagnaChip $0.18{mu}m$ library and can run at 125 MHz.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.169-172
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• 2000

This paper describes design of cryptographic processor which can execute SEED, DES, and triple DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has I unrolled loop structure with hardware sharing and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation, the precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O technique is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is designed using 2.5V 0.25 $\mu\textrm{m}$ CMOS technology and consists of about 34.8K gates. Its peak performances is about 250 Mbps under 100 Mhz ECB SEED mode and 125 Mbps under 100 Mhz triple DES mode.

• 한국신재생에너지학회:학술대회논문집
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• 2005.06a
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• pp.273-276
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• 2005

Performance analysis of a solid oxide fuel cell/micro gas turbine hybrid system is conducted at design-point and part-load conditions and its results are discussed in this study. With detailed considerations of the heat and mass transfer phenomena along various flow streams of the SOFC, the analysis based on a quasi-2D model reasonably predicts its performance at the design-point operating conditions. In case of part-load operations, performance of the hybrid system to three different operation modes(fuel only control, speed control, and VIGV control) is compared. It is found that the simultaneous control of both supplied fuel and air to the system with a variable MGT rotational speed mode is the optimum choice for the high performance operation. And then, the dynamic characteristics of a solid oxide fuel cell are briefly introduced.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2006.05a
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• pp.232-237
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• 2006

Operation deflection shapes(ODS) is defined as a motion of structure at particular frequency. The ODS is eligible to show any types of structural motions while the modes supply solutions only to linear and stationary motion. The principal vibration source of an auto teller machine(ATM) case was occurred due to resonance which was found by modal analysis. To reduce the vibration of ATM case, the motion of the case was visualized using ODS analysis, which can suggest how to modify the structure. As a result the vibration of the ATM case was greatly reduced with a stiffening bar between the opposite plates.

• Journal of international Conference on Electrical Machines and Systems
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• v.2 no.2
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• pp.202-215
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• 2013

This paper proposes a SEPIC-input, self-driven, active clamp ZVS converter, where an auxiliary winding and a RC delay circuit are employed to drive the active clamp switch and to achieve asymmetrical duty control without any other extra circuits. Based on the fixed dead time and the resonance between capacitors and inductors, both the main switch and the auxiliary switch can rule the ZVS operation. Detailed operation modes are presented to illustrate the self-driven and ZVS principles. Furthermore, an accurate state-space model and the transfer functions of the proposed converter have been presented and analyzed in order to optimize dynamic performance. The model provides efficient prediction of converter operations. Experimental results, based on a prototype with 80V input and 15V/20A output, are discussed to verify the transient and steady performance of the proposed converter.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1720-1728
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• 2018

This paper proposes a novel soft starting algorithm by using PWM inverter technique to control an amplitude of the motor starting current at a single-phase induction motor (SPIM). Traditional SPIM starting methods such as a Split-Phase, Capacitor-Start, Permanent-Split Capacitor (PSC), Capacitor-Start Capacitor-Run (CSCR), basically cannot control the magnitude of starting current due to the fixed system structures. Therefore, in this paper, a soft starting algorithm based on a proportional resonant (PR) control with a variable and constant frequency is proposed to reduce the inrush current and starting up time. In addition, a transition algorithm for operation modes is devised to generate a constant voltage and constant frequency (CVCF). The validity and effectiveness of the proposed soft starting method and transition algorithm are verified through experimental results.

• Proceedings of the Korea Multimedia Society Conference
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• 2000.04a
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• pp.117-120
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• 2000

This paper describe VLSL design of crytographic processor which can execute triple DES and DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has 1 unrolled loop structure without pipeline and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation , the key precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O techniques is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is implemented using Altera EPF10K40RC208-4 devices and has peak performance of about 75 Mbps under 20 Mhz ECB DES mode and 25 Mbps uder 20 Mhz triple DES mode.

• Journal of Power Electronics
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• v.9 no.5
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• pp.809-821
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• 2009

This paper proposes a new phase-shift full-bridge DC-DC converter by applying energy recovery circuits to a conventional full-bridge DC-DC converter in plasma display panel applications. The converter can achieve soft-switching in main-switches by an extra auxiliary resonant network even with the wide operating condition of both output load and input voltage. The un-coupled design guidelines to the main bridge-leg component parameters for soft-switching operation contribute to conduction loss reduction in the transformer primary side leading to efficiency improvement. The auxiliary switches in the resonant network also operate in zero-current switching. This paper analyzes the operation modes of the proposed scheme and presents the key design guidelines through steady state analysis. Also, the paper verifies the validity of the circuits by hardware experiments with a 1kW DC/DC converter prototype.

• International Journal of Industrial Entomology and Biomaterials
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• v.27 no.2
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• pp.322-325
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• 2013

In the present study, we report that the selection of operation mode is important to take the full advantage of nanofibrous membrane in enzyme immobilization. Silk fibroin nanofibrous membrane has been prepared by electrospinning, and a-chymotrypsin was immobilized as a model enzyme. When the immobilized enzyme was operated in the membrane reactor mode, the Michaelis constant, Km, was lower and the Vmax was higher compared to the batch reactor mode. No concentration gradient was observed in the membrane reactor mode and the immobilized enzyme was stable even after 7 times of re-use. Our results suggests that the enzyme immobilized nanofibrous membrane should be operated in the membrane reactor mode rather than in the bath reactor mode.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2007.05a
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• pp.340-343
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• 2007

In this paper, we present our method to reduce vibration of the base plate of a refrigerator by avoiding resonance between base plate and compressor operation. To verify the modes of the base plate, FE models of the base plate with free-free condition and applied boundary condition were built and validated by results from experimental modal analysis. Operating Deflection Shape analysis was applied to find the sensitive area on the base plate during compressor operation. In optimization process, Finite Difference Method - based sensitivity analysis is used to detect the most sensitive area. Finally, based on this numerical result, we will make beads on the base plate to reduce vibration of refrigerator.