• Journal of IKEEE
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• v.25 no.1
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• pp.156-167
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• 2021

In this paper, we propose a digital transceiver unit design for in-building of 5G optical repeaters that extends the coverage of 5G mobile communication network services and connects to a stable wireless network in a building. The digital transceiver unit for driving the proposed 5G optical repeater is composed of 4 blocks: a signal processing unit, an RF transceiver unit, an optical input/output unit, and a clock generation unit. The signal processing unit plays an important role, such as a combination of a basic operation of the CPRI interface, a 4-channel antenna signal, and response to external control commands. It also transmits and receives high-quality IQ data through the JESD204B interface. CFR and DPD blocks operate to protect the power amplifier. The RF transmitter/receiver converts the RF signal received from the antenna to AD, is transmitted to the signal processing unit through the JESD204B interface, and DA converts the digital signal transmitted from the signal processing unit to the JESD204B interface and transmits the RF signal to the antenna. The optical input/output unit converts an electric signal into an optical signal and transmits it, and converts the optical signal into an electric signal and receives it. The clock generator suppresses jitter of the synchronous clock supplied from the CPRI interface of the optical input/output unit, and supplies a stable synchronous clock to the signal processing unit and the RF transceiver. Before CPRI connection, a local clock is supplied to operate in a CPRI connection ready state. XCZU9CG-2FFVC900I of Xilinx's MPSoC series was used to evaluate the accuracy of the digital transceiver unit for driving the 5G optical repeater proposed in this paper, and Vivado 2018.3 was used as the design tool. The 5G optical repeater digital transceiver unit proposed in this paper converts the 5G RF signal input to the ADC into digital and transmits it to the JIG through CPRI and outputs the downlink data signal received from the JIG through the CPRI to the DAC. And evaluated the performance. The experimental results showed that flatness, Return Loss, Channel Power, ACLR, EVM, Frequency Error, etc. exceeded the target set value.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.670-680
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• 2010

A low power single-chip CMOS receiver for 60 GHz mobile application are proposed in this paper. The single-chip receiver consists of a 4-stage current re-use LNA with under 4 dB NF, Cgs compensating resistive mixer with -9.4 dB conversion gain, Ka-band low phase noise VCO with -113 dBc/Hz phase noise at 1 MHz offset from 26.89 GHz, high-suppression frequency doubler with -0.45 dB conversion gain, and 2-stage current re-use drive amplifier. The size of the fabricated receiver using a standard 0.13 ${\mu}m$ CMOS technology is 2.67 mm$\times$0.75 mm including probing pads. An RF bandwidth is 6.2 GHz, from 55 to 61.2 GHz and an LO tuning range is 7.14 GHz, from 48.45 GHz to 55.59 GHz. The If bandwidth is 5.25 GHz(4.75~10 GHz) The conversion gain and input P1 dB are -9.5 dB and -12.5 dBm, respectively, at RF frequency of 59 GHz. The proposed single-chip receiver describes very good noise performances and linearity with very low DC power consumption of only 21.9 mW.