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High Performance Data Cache Memory Architecture (고성능 데이터 캐시 메모리 구조)

  • Kim, Hong-Sik;Kim, Cheong-Ghil
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.9 no.4
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    • pp.945-951
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    • 2008
  • In this paper, a new high performance data cache scheme that improves exploitation of both the spatial and temporal locality is proposed. The proposed data cache consists of a hardware prefetch unit and two sub-caches such as a direct-mapped (DM) cache with a large block size and a fully associative buffer with a small block size. Spatial locality is exploited by fetching and storing large blocks into a direct mapped cache, and is enhanced by prefetching a neighboring block when a DM cache hit occurs. Temporal locality is exploited by storing small blocks from the DM cache in the fully associative buffer according to their activity in the DM cache when they are replaced. Experimental results on Spec2000 programs show that the proposed scheme can reduce the average miss ratio by $12.53%\sim23.62%$ and the AMAT by $14.67%\sim18.60%$ compared to the previous schemes such as direct mapped cache, 4-way set associative cache and SMI(selective mode intelligent) cache[8].

Improvement of the Avoidance Performance of TCAS-II by Employing Kalman Filter (Kalman Filter를 적용한 TCAS-II 충돌회피 성능 개선)

  • Jun, Byung-Kyu;Lim, Sang-Seok
    • Journal of Advanced Navigation Technology
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    • v.15 no.6
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    • pp.986-993
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    • 2011
  • In this paper we consider the problem of the existing TCAS-II systems that fail to be satisfactory solution to mid-air collisions (MACs) and near mid-air collisions (NMACs or near misses). This is attributed to the fact that the earlier studies on the collision avoidance mainly have focused on determination logic of avoidance direction and vertical speed, reversal of the avoidance direction, multiple aircraft geometry, and availability in certain air spaces. But, the influence of sensor measurement errors on the performance of collision avoidance was not properly taken into account. Here we propose a new TCAS algorithm by using Kalman filter instead of '${\alpha}-{\beta}$' tracker to improve the avoidance performance under the influence of barometric sensor errors due to air-temperature, pressure leaks, static source error correction, etc.

Alternative Version Concurrency Control Method for firm real-time database systems (대체 버전을 이용한 펌 실시간 데이터베이스 동시성 제어 방법)

  • Hong, Dong-Kweon
    • The Transactions of the Korea Information Processing Society
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    • v.5 no.6
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    • pp.1377-1389
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    • 1998
  • Firm real time transactions on firm real-time database systems arc discarded when they miss their deadlines. as there is no value to completing them after they miss their deadlines. Several approaches that exploit the semantics of firm deadlines to improve the performance of firm real-time database systems have been proposed in the literature. They are based Oil locking or optimistic concurrency controL The performance comparisons of the two approaches differ with svstems load. In this paper. we develop a novel policy termed stop/resume deferred restart policy, and a concurrency control algorithm based on the policy (temled Altcmativc Version Concurrency Contro). When conflicts : due to Pliority) occur our algmithm maintains the immediately restarted VerSlOn as wpll as the stopped version of a transaction in order to use one of the two to meet the firm deadline. At last we show that our policy generates scrializable schedules and show tbat our algorithm performs better than the traditionally used method for wide ranges of the system load for firm deadline transaction.

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Timing Optimization of Real-Time System Design for Embedded Systems (Embedded System Design을 위한 Real-Time System의 최적화된 Timing효과의 구현)

  • Park, Eun-Jung;Jeong, Tai-Kyeong
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.3
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    • pp.564-570
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    • 2006
  • This paper presents a new real-time system design methodology for embedded system as well as event-driven real time application. It is required to implement a deadline handling mechanism in order to satisfy a large-scale distributed real time application. When we design real time system, it has handled a deadline and is important to measure / control a timing issue. These timing constraints usually associated with an interface between model and system. There are many case tools that supporting a real time application, for example, UML, graphic language for designing real time system, but they cannot provide efficient way to handle deadline miss. Therefore, users have to design deadline handler manually when they need to use it. This paper contributes solving the problems of user-level deadline handling for an embedded system. Also, it also discusses an efficient deadline handler design mechanism using on RoseRT, which is a graphical CASE tool supporting from UML.

Clowns in David Copperfield (『데이빗 코퍼필드』에서의 광대들)

  • Park, Geumhee
    • English & American cultural studies
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    • v.9 no.1
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    • pp.185-219
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    • 2009
  • This article aims to illuminate the comic characters and their humor in Dickens's novel David Copperfield in Bakhtinian point, and to clarify what the humorous characteristics are, and how they contribute to his reinforcement of socially critical messages in this novel. So far this novel has been called the only one of Dickens's comic novels, even though it includes lots of social critical meanings. But it is true that Dickensian critics couldn't make sure of the clear reasons why it is both very interesting and critical. Furthermore, it is also true that this novel has been criticized as a clumsy one in the realistic, psycho-analytic, dramatic angle. This approach to Dickensian comic characters through Bakhtinian fool, clown, and rogue concepts here could make up for or correct such criticisms, and reevaluate Dickens's humor and social criticisms in the context of general public culture. Bakhtin believes oppression by social ideologies prevent us from having good mutual relationships and divides our society. He thinks laughter liberates us from such oppression and restores our good relationships. As he applied his concepts based on the laughter of Middle Ages to Rabelais's novels, and examined what the authentically liberating power in Rabelais's laughter is, this article could clarify the liberating power of laughter by Dickens's comic characters, such as Mr and Mrs Micawber, Dick, Miss Betsey Trotwood and Miss Mowcher. In this novel, they often lead comic happenings, and such happenings are very similar to carnival-amusements including burning the dummy of the czar who has oppressed his or her citizenry. Especially, Dickens's comic characters's social criticisms, in the case of this novel, contain many complaints of social marginers, even though he has been labelled as being conservative politically. They always criticize the ideological absurdities in their society through the humorous words and behaviors in their comic happenings, like those of a carnival fool or clown in his or her amusements. This shows Dickens achieves both laughter and social criticism in David Copperfield by using Rabelaisian characterization-devices based on his general public culture. Like Bakhtin and Rabelais, Dickens seems to have believed that when we all truly liberate ourselves from the oppression of social ideologies, we can have desirable relationships between ourselves, and also solve social problems positively.

Cinematic Representation of Child Abuse and the Maternal Myth: A Narrative Analysis of and (아동학대의 재현과 모성 신화: <미쓰백>과 <어린 의뢰인>의 서사 분석을 중심으로)

  • Lee, Sohyun
    • The Journal of the Korea Contents Association
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    • v.22 no.6
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    • pp.194-207
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    • 2022
  • Amid growing social interest in child abuse, and announced the seriousness of child abuse crimes and aroused public interest in related issues. Based on true stories and characters, both films created unique narratives about child abuse cases, but drew on the traditional representation and discursive construction of child abuse news articles. By setting the stepmother as the perpetrator and the father as the neglecter, the gender role of women as primary caregiver was reconfirmed and the stereotypical image of the 'evil stepmother' in popular narratives was exploited. The cinematic reenactment of the evil stepmother not only highlighted the normative family discourse, but also reinforced the maternal myth by emphasizing the binary opposition between the evil stepmother and the lost birth mother.

A Validation Study on Korean version of Heterophobia scale for Gay male (한국판 남성 동성애자의 이성애불편감(Heterophobia) 척도(K-HGM)의 타당화)

  • Kim Joon Hyun;Yu Kum Lan
    • Korean Journal of Culture and Social Issue
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    • v.29 no.1
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    • pp.25-51
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    • 2023
  • The purpose of the study was to validate the Korean version of the Heterophobia Scale for Gay Male (HGM). Heterophobia refers to the rejection, fear, and avoidance that sexual minorities feel against of heterosexuals. The three subscales of HGM assesses the unease/avoidance, disconnectedness, and expected rejection fromwith heterosexual male. To validate the Korean HGM, item translation, item analysis, and exploratory factor analysis were conducted. From the Using exploratory factor analysis of the Korean version of the HGM(N=213), per 13 items, a 3-factor model consisting of 13 items wereas determined. The Cconfirmatory factor analysis supported the goodness of fit of the 3-factor structure of the K-HGM (N=153) and showed adequate model fit, K-HGM showed adequate the internal consistency, convergent validity, discriminant validity and Criterion validity was good with other related scales (K-SOMS, K-MISS-G, SDS-9, and RS). In conclusion, the K-HGM is a valid measure of heterophobia for gay male within the Korean population. Based on the findings, implications, practical use, limitations, and suggestions for future study are discussed.

CC-GiST: A Generalized Framework for Efficiently Implementing Arbitrary Cache-Conscious Search Trees (CC-GiST: 임의의 캐시 인식 검색 트리를 효율적으로 구현하기 위한 일반화된 프레임워크)

  • Loh, Woong-Kee;Kim, Won-Sik;Han, Wook-Shin
    • The KIPS Transactions:PartD
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    • v.14D no.1 s.111
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    • pp.21-34
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    • 2007
  • According to recent rapid price drop and capacity growth of main memory, the number of applications on main memory databases is dramatically increasing. Cache miss, which means a phenomenon that the data required by CPU is not resident in cache and is accessed from main memory, is one of the major causes of performance degradation of main memory databases. Several cache-conscious trees have been proposed for reducing cache miss and making the most use of cache in main memory databases. Since each cache-conscious tree has its own unique features, more than one cache-conscious tree can be used in a single application depending on the application's requirement. Moreover, if there is no existing cache-conscious tree that satisfies the application's requirement, we should implement a new cache-conscious tree only for the application's sake. In this paper, we propose the cache-conscious generalized search tree (CC-GiST). The CC-GiST is an extension of the disk-based generalized search tree (GiST) [HNP95] to be tache-conscious, and provides the entire common features and algorithms in the existing cache-conscious trees including pointer compression and key compression techniques. For implementing a cache-conscious tree based on the CC-GiST proposed in this paper, one should implement only a few functions specific to the cache-conscious tree. We show how to implement the most representative cache-conscious trees such as the CSB+-tree, the pkB-tree, and the CR-tree based on the CC-GiST. The CC-GiST eliminates the troublesomeness caused by managing mire than one cache-conscious tree in an application, and provides a framework for efficiently implementing arbitrary cache-conscious trees with new features.

The Early Write Back Scheme For Write-Back Cache (라이트 백 캐쉬를 위한 빠른 라이트 백 기법)

  • Chung, Young-Jin;Lee, Kil-Whan;Lee, Yong-Surk
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.11
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    • pp.101-109
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    • 2009
  • Generally, depth cache and pixel cache of 3D graphics are designed by using write-back scheme for efficient use of memory bandwidth. Also, there are write after read operations of same address or only write operations are occurred frequently in 3D graphics cache. If a cache miss is detected, an access to the external memory for write back operation and another access to the memory for handling the cache miss are operated simultaneously. So on frequent cache miss situations, as the memory access bandwidth limited, the access time of the external memory will be increased due to memory bottleneck problem. As a result, the total performance of the processor or the IP will be decreased, also the problem will increase peak power consumption. So in this paper, we proposed a novel early write back cache architecture so as to solve the problems issued above. The proposed architecture controls the point when to access the external memory as to copy the valid data block. And this architecture can improve the cache performance with same hit ratio and same capacity cache. As a result, the proposed architecture can solve the memory bottleneck problem by preventing intensive memory accesses. We have evaluated the new proposed architecture on 3D graphics z cache and pixel cache on a SoC environment where ARM11, 3D graphic accelerator and various IPs are embedded. The simulation results indicated that there were maximum 75% of performance increase when using various simulation vectors.

Implementation and Performance Analysis of Efficient Packet Processing Method For DPI (Deep Packet Inspection) System using Dual-Processors (듀얼 프로세서 기반 DPI (Deep Packet Inspection) 엔진을 위한 효율적 패킷 프로세싱 방안 구현 및 성능 분석)

  • Yang, Joon-Ho;Han, Seung-Jae
    • The KIPS Transactions:PartC
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    • v.16C no.4
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    • pp.417-422
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    • 2009
  • Implementation of DPI(Deep Packet Inspection) system on a general purpose multiprocessor platform is an attractive option from the implementation cost point of view, since it does not require high-cost customized hardware. Load balancing has been considered as a primary means to achieve high performance in multi processor systems. We claim, however, that in case of DPI system design simply balancing the load of each processor does not necessarily yield the highest system performance. Instead, we propose a method in which tasks are allocated to processors based on their functions. We implemented the proposed method in dual processor Linux system and compare its performance with the existing load balancing methods. Under the proposed method, one processor is dedicated to deal with interrupt handling and generic packet processing, while another processor is dedicated to DPI processing. According to experimental results, the proposed scheme outperforms the existing schemes by 60%, mainly because of the reduction of cache miss and spin lock occurrences.