• Title/Summary/Keyword: Mismatch Compensation

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Illumination Mismatch Compensation Algorithm based on Layered Histogram Matching by Using Depth Information (깊이 정보에 따른 레이어별 히스토그램 매칭을 이용한 조명 불일치 보상 기법)

  • Lee, Dong-Seok;Yoo, Ji-Sang
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.8C
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    • pp.651-660
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    • 2010
  • In this paper, we implement an efficient histogram-based prefiltering to compensate the illumination mismatches in regions between neighboring views. In multi-view video, such illumination disharmony can primarily occur on account of different camera location and orientation and an imperfect camera calibration. This discrepancy can cause the performance decrease of multi-view video coding(MVC) algorithm. A histogram matching algorithm can be exploited to make up for these differences in a prefiltering step. Once all camera frames of a multi-view sequence are adjusted to a predefined reference through the histogram matching, the coding efficiency of MVC is improved. However general frames of multi-view video sequence are composed of several regions with different color composition and their histogram distribution which are mutually independent of each other. In addition, the location and depth of these objects from sequeuces captured from different cameras can be different with different frames. Thus we propose a new algorithm which classify a image into several subpartitions by its depth information first and then histogram matching is performed for each region individually. Experimental results show that the compression ratio for the proposed algorithm is improved comparing with the conventional image-based algorithms.

Probability of Early Retirement Among Emergency Physicians

  • Shin, Jaemyeong;Kim, Yun Jeong;Kim, Jong Kun;Lee, Dong Eun;Moon, Sungbae;Choe, Jae Young;Lee, Won Kee;Lee, Hyung Min;Cho, Kwang Hyun
    • Journal of Preventive Medicine and Public Health
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    • v.51 no.3
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    • pp.154-162
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    • 2018
  • Objectives: Early retirement occurs when one's job satisfaction suffers due to employment mismatch resulting from factors such as inadequate compensation. Medical doctors report high levels of job stress and burnout relative to other professionals. These levels are highest among emergency physicians (EPs), and despite general improvements in their working conditions, early retirement continues to become more common in this population. The purpose of this study was to identify the factors influencing EPs intention to retire early and to develop a probability equation for its prediction. Methods: A secondary analysis of data from the 2015 Korean Society of Emergency Physicians Survey was performed. The variables potentially influencing early retirement were organized into personal characteristics, extrinsic factors, and intrinsic factors. Logistic regression analysis was performed to identify risk factors and to develop a probability equation; these findings were then arranged in a nomogram. Results: Of the 377 survey respondents included in the analysis, 48.0% intended to retire early. Risk factors for early retirement included level of satisfaction with the specialty and its outlook, slanderous reviews, emergency room safety, health status, workload intensity, age, and hospital type. Intrinsic factors (i.e., slanderous reviews and satisfaction with the specialty and its outlook) had a stronger influence on early retirement than did extrinsic factors. Conclusions: To promote career longevity among EPs, it is vital to improve emergency room safety and workload intensity, to enhance medical professionalism through a stronger vision of emergency medicine, and to strengthen the patient-doctor relationship.

Low Complexity Frequency Offset Estimation Using Partial Correlation (부분상관을 이용한 저 복잡도의 주파수 오차 추정기법)

  • Park, Ji-Eun;Jeong, YeongWeon;Song, InJae;Jeong, Eui-Rim
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.8
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    • pp.1861-1868
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    • 2014
  • In wireless communication systems, a frequency offset exist at the received signal due to the transmitter-receiver oscillator mismatch and Doppler effect in mobile environments. Those offsets rotate the received signal's phase and degrade the receiver performance. Hence, estimation and compensation of the frequency offset is crucial at the receiver. This paper proposes a new frequency offset estimation technique based on partial correlation. The proposed method requires less computational complexity than that of the conventional method. In addition, since the proposed one can estimate a wide range of frequency offset without estimation accuracy loss, the application of the method is desirable for the communication environments that have a large frequency offset. In order to verify the performance of our proposed scheme, a series of computer simulations have been carried out and compared against those of the conventional method.

A 1.1V 12b 100MS/s 0.43㎟ ADC based on a low-voltage gain-boosting amplifier in a 45nm CMOS technology (45nm CMOS 공정기술에 최적화된 저전압용 이득-부스팅 증폭기 기반의 1.1V 12b 100MS/s 0.43㎟ ADC)

  • An, Tai-Ji;Park, Jun-Sang;Roh, Ji-Hyun;Lee, Mun-Kyo;Nah, Sun-Phil;Lee, Seung-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.7
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    • pp.122-130
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    • 2013
  • This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.

Design and Performance Evaluation of the DFT-Spread OFDM Communication System for Phase Noise Compensation and PAPR Reduction (위상 잡음 보상과 PAPR 저감을 고려한 DFT-Spread OFDM 통신 시스템 설계와 성능 평가)

  • Li Ying-Shan;Kim Nam-Il;Kim Sang-Woo;Ryu Heung-Gyoon
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.17 no.7 s.110
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    • pp.638-647
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    • 2006
  • Recently, the DFT-Spread OFDM has been studied for the PAPR reduction. However, the DFT-Spread OFDM produces more ICI and SCI problems than OFDM because phase offset mismatch of the DFT spreading code results from the random phase noise in the oscillator. In this paper, at first, phase noise influence on the DFT-Spread OFDM system is theoretically analyzed in terms of the BER performance. Then, the conventional ICI self-cancellation methods are discussed and two kinds of ICI self-cancellation methods are newly proposed. Lastly, a new DFT-Spread OFDM system which selectively adopts the ICI self-cancellation technique is proposed to resolve the interference problem and PAPR reduction simultaneously. Proposednew DFT-Spread OFDM system can minimize performance degradation caused by phase noise, and still maintain the low PAPR property. Among the studied methods, DFT-Spread OFDM with data-conjugate method or newly proposed symmetric data-conjugate method show the significant performance improvements, compared with the DFT-Spread OFDM without ICI self-cancellation schemes. The data-conjugate method is slightly better than symmetric data-conjugate method.

An Area-Efficient DC-DC Converter with Poly-Si TFT for System-On-Glass (System-On-Glass를 위한 Poly-Si TFT 소 면적 DC-DC 변환회로)

  • Lee Kyun-Lyeol;Kim Dae-June;Yoo Changsik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.2 s.332
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    • pp.1-8
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    • 2005
  • An area-efficient DC-DC voltage up-converter in a poly-Si TFT technology for system-on-glass is described which provides low-ripple output. The voltage up-converter is composed of charge-pumping circuit, comparator with threshold voltage mismatch compensation, oscillator, buffer, and delay circuit for multi-phase clock generation. The low ripple output is obtained by multi-phase clocking without increasing neither clock frequency nor filtering capacitor The measurement results have shown that the ripple on the output voltage with 4-phase clocking is 123mV, while Dickson and conventional cross-coupled charge pump has 590mV and 215mV voltage ripple, respectively, for $Rout=100k\Omega$, Cout-100pF, and fclk=1MHz. The filtering capacitor required for 50mV ripple voltage is 1029pF and 575pF for Dickson and conventional cross-coupled structure, for Iout=100uA, and fclk=1MHz, while the proposed multi-phase clocking DC-DC converter with 4-phase and 6-phase clocking requires only 290pF and 157pF, respectively. The efficiency of conventional and the multi-phase clocking DC-DC converter with 4-phase clocking is $65.7\%\;and\;65.3\%$, respectively, while Dickson charge pump has $59\%$ efficiency.

A 3.2Gb/s Clock and Data Recovery Circuit without Reference Clock for Serial Data Communication (시리얼 데이터 통신을 위한 기준 클록이 없는 3.2Gb/s 클록 데이터 복원회로)

  • Kim, Kang-Jik;Jung, Ki-Sang;Cho, Seong-Ik
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.46 no.2
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    • pp.72-77
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    • 2009
  • In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

Direct Imaging of Polarization-induced Charge Distribution and Domain Switching using TEM

  • O, Sang-Ho
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.08a
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    • pp.99-99
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    • 2013
  • In this talk, I will present two research works in progress, which are: i) mapping of piezoelectric polarization and associated charge density distribution in the heteroepitaxial InGaN/GaN multi-quantum well (MQW) structure of a light emitting diode (LED) by using inline electron holography and ii) in-situ observation of the polarization switching process of an ferroelectric Pb(Zr1-x,Tix)O3 (PZT) thin film capacitor under an applied electric field in transmission electron microscope (TEM). In the first part, I will show that strain as well as total charge density distributions can be mapped quantitatively across all the functional layers constituting a LED, including n-type GaN, InGaN/GaN MQWs, and p-type GaN with sub-nm spatial resolution (~0.8 nm) by using inline electron holography. The experimentally obtained strain maps were verified by comparison with finite element method simulations and confirmed that not only InGaN QWs (2.5 nm in thickness) but also GaN QBs (10 nm in thickness) in the MQW structure are strained complementary to accommodate the lattice misfit strain. Because of this complementary strain of GaN QBs, the strain gradient and also (piezoelectric) polarization gradient across the MQW changes more steeply than expected, resulting in more polarization charge density at the MQW interfaces than the typically expected value from the spontaneous polarization mismatch alone. By quantitative and comparative analysis of the total charge density map with the polarization charge map, we can clarify what extent of the polarization charges are compensated by the electrons supplied from the n-doped GaN QBs. Comparison with the simulated energy band diagrams with various screening parameters show that only 60% of the net polarization charges are compensated by the electrons from the GaN QBs, which results in the internal field of ~2.0 MV cm-1 across each pair of GaN/InGaN of the MQW structure. In the second part of my talk, I will present in-situ observations of the polarization switching process of a planar Ni/PZT/SrRuO3 capacitor using TEM. We observed the preferential, but asymmetric, nucleation and forward growth of switched c-domains at the PZT/electrode interfaces arising from the built-in electric field beneath each interface. The subsequent sideways growth was inhibited by the depolarization field due to the imperfect charge compensation at the counter electrode and preexisting a-domain walls, leading to asymmetric switching. It was found that the preexisting a-domains split into fine a- and c-domains constituting a $90^{\circ}$ stripe domain pattern during the $180^{\circ}$ polarization switching process, revealing that these domains also actively participated in the out-of-plane polarization switching. The real-time observations uncovered the origin of the switching asymmetry and further clarified the importance of charged domain walls and the interfaces with electrodes in the ferroelectric switching processes.

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