• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.423.1-423.1
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• 2014

본 발표에서는 실리콘 이종접합 태양전지에서 중요한 실리콘 웨이퍼 표면/계면 제어에 대하여 발표한다. 다시 말하여, 실리콘 웨이퍼 기판 세정공정 변화에 따른 실리콘 웨이퍼 표면의 소수전하수명(minority carrier lifetime, MCLT) 및 태양전지 소자특성 변화에 대하여 연구하였다. 구체적으로, 실리콘 웨이퍼 클리닝 최초단계로써 KOH damage etching 공정을 도입할 때, 이후 클리닝 공정을 통일하여 적용한 웨이퍼 표면의 MCLT 및 상기 웨이퍼를 이용하여 플라즈마 화학기상증착법(PECVD)을 통하여 제작한 태양전지 소자 효율은 KOH etching 시간이 10분일 때 최대치에 도달한 후 감소하였다. 또한, RCA1, RCA2, Piranha로 이루어진 웨이퍼 클리닝 단계의 사이에, 또는 맨 마지막에 묽힌 불산용액(DHF, 5 %) 처리를 하여 표면 산화막 제거 및 수소종단처리를 하여 기판의 passivation 특성을 향상시키고자 할 때, 불산용액 처리 순서에 따른 웨이퍼 표면의 MCLT 및 태양전지 소자 효율을 비교하였다. 그 결과, 묽은불산용액을 클리닝 단계 사이에 적용하였을 때의 MCLT 및 태양전지 소자의 특성이 더 우수하였다.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2010년도 춘계학술대회 초록집
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• pp.99.2-99.2
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• 2010

This paper investigates the dependence of a-Si:H/c-Si passivation and heterojunction solar cell performances on various cleaning processes of silicon wafer and surface morphology. It is observed that passivation quality of a-Si:H thin-films on c-Si wafer highly depends on wafer surface conditions. The MCLT(Minority carrier life time) of wafer incorporating intrinsic (i) a-Si:H as a passivation layer shows sensitive variation with cleaning process and surface morpholgy. By applying improved cleaning processes and surface morphology we can obtain the MCLT of $200{\mu}sec$ after H-termination and above 1.5msec after i a-Si:H thin film deposition, which has implied open circuit voltage of 0.720V.

• 한국전기전자재료학회논문지
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• 제30권3호
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• pp.139-143
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• 2017

N-type crystalline silicon solar cells have high metal impurity tolerance and higher minority carrier lifetime that increases conversion efficiency. However, junction quality between the boron diffused layer and the n-type substrate is more important for increased efficiency. In this paper, the current status and prospects for boron diffused layers in N-type crystalline silicon solar cell applications are described. Boron diffused layer formation methods (thermal diffusion and co-diffusion using $a-SiO_X:B$), boron rich layer (BRL) and boron silicate glass (BSG) reactions, and analysis of the effects to improve junction characteristics are discussed. In-situ oxidation is performed to remove the boron rich layer. The oxidation process after diffusion shows a lower B-O peak than before the Oxidation process was changed into $SiO_2$ phase by FTIR and BRL. The $a-SiO_X:B$ layer is deposited by PECVD using $SiH_4$, $B_2H_6$, $H_2$, $CO_2$ gases in N-type wafer and annealed by thermal tube furnace for performing the P+ layer. MCLT (minority carrier lifetime) is improved by increasing $SiH_4$ and $B_2H_6$. When $a-SiO_X:B$ is removed, the Si-O peak decreases and the B-H peak declines a little, but MCLT is improved by hydrogen passivated inactive boron atoms. In this paper, we focused on the boron emitter for N-type crystalline solar cells.

• 한국세라믹학회지
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• 제49권6호
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• pp.637-641
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• 2012

Due to its high production cost and relatively high energy consumption during the Siemens process, poly-silicon makers have been continuously and eagerly sought another silicon route for decades. One candidate that consumes less energy and has a simpler acidic and metallurgical purification procedure is upgraded metallurgical-grade (UMG) silicon. Owing to its low purity, UMG silicon often requires special steps to minimize the impurity effects and to remove or segregate the metal atoms in the bulk and to remove interfacial defects such as precipitates and grain boundaries. A process often called the 'gettering process' is used with phosphorus diffusion in this experiment in an effort to improve the performance of silicon solar cells using UMG silicon. The phosphorous gettering processes were optimized and compared to the standard POCl process so as to increase the minority carrier lifetime(MCLT) with the duration time and temperature as variables. In order to analyze the metal impurity concentration and distribution, secondary ion mass spectroscopy (SIMS) was utilized before and after the phosphorous gettering process.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2011년도 춘계학술대회 초록집
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• pp.129.1-129.1
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• 2011

a-Si:H/c-Si 구조의 이종접합 태양전지 전면 투명전도막으로 Indium tin oxide(ITO) 박막의 조건에 따라 태양전지 특성을 연구하였다. ITO 박막은 파우더 타겟으로 마그네트론 스퍼터링 방식으로 성막하였고, 증착 온도(Ts)에 따라 전기적, 광학적 특성을 비교, 분석하였다. 기판 증착 온도가 증가할수록 박막의 저항이 낮아지는 것으로 나타났으며 $350^{\circ}C$ 조건에서 가장 낮은 저항($34.2{\Omega}$/sq)을 보였다. 투과도 또한 기판 증착 온도가 올라갈수록 전반적인 향상을 나타냈다. a-Si:H/c-Si 기판의 MCLT(minority carrier lifetime)는 $350^{\circ}C$에서 최적($359{\mu}s$)의 결과를 나타냈다. 그 이상의 기판 온도에서는 오히려 감소하였는데, 이는 높은 온도에서의 a-Si:H/c-Si 계면의 열손상으로 판단된다.

• Nuclear Engineering and Technology
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• 제49권1호
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• pp.209-215
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• 2017

Fast neutron irradiation was used to improve the switching speed of a 600-V nonpunch-through insulated gate bipolar transistor. Fast neutron irradiation was carried out at 30-MeV energy in doses of $1{\times}10^8n/cm^2$, $1{\times}10^9n/cm^2$, $1{\times}10^{10}n/cm^2$, and $1{\times}10^{11}n/cm^2$. Electrical characteristics such as current-voltage, forward on-state voltage drop, and switching speed of the device were analyzed and compared with those prior to irradiation. The on-state voltage drop of the initial devices prior to irradiation was 2.08 V, which increased to 2.10 V, 2.20 V, 2.3 V, and 2.4 V, respectively, depending on the irradiation dose. This effect arises because of the lattice defects generated by the fast neutrons. In particular, the turnoff delay time was reduced to 92 nanoseconds, 45% of that prior to irradiation, which means there is a substantial improvement in the switching speed of the device.

• 한국재료학회지
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• 제20권4호
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• pp.210-216
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• 2010

This paper investigates the dependence of a-Si:H/c-Si passivation and heterojunction solar cell performances on various cleaning processes of silicon wafers. It is observed that the passivation quality of a-Si:H thin-films on c-Si wafers depends highly on the initial H-termination properties of the wafer surface. The effective minority carrier lifetime (MCLT) of highly H-terminated wafer is beneficial for obtaining high quality passivation of a-Si:H/c-Si. The wafers passivated by p(n)-doped a-Si:H layers have low MCLT regardless of the initial H-termination quality. On the other hand, the MCLT of wafers incorporating intrinsic (i) a-Si:H as a passivation layer shows sensitive variation with initial cleaning and H-termination schemes. By applying the improved cleaning processes, we can obtain an MCLT of $100{\mu}sec$ after H-termination and above $600{\mu}sec$ after i a-Si:H thin film deposition. By adapting improved cleaning processes and by improving passivation and doped layers, we can fabricate a-Si:H/c-Si heterojunction solar cells with an active area conversion efficiency of 18.42%, which cells have an open circuit voltage of 0.670V, short circuit current of $37.31\;mA/cm^2$ and fill factor of 0.7374. These cells show more than 20% pseudo efficiency measured by Suns-$V_{oc}$ with an elimination of series resistance.

• 한국재료학회지
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• 제23권1호
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• pp.35-40
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• 2013

In this study, the influence on the surface passivation properties of crystalline silicon according to silicon wafer thickness, and the correlation with a-Si:H/c-Si heterojunction solar cell performances were investigated. The wafers passivated by p(n)-doped a-Si:H layers show poor passivation properties because of the doping elements, such as boron(B) and phosphorous(P), which result in a low minority carrier lifetime (MCLT). A decrease in open circuit voltage ($V_{oc}$) was observed when the wafer thickness was thinned from $170{\mu}m$ to $50{\mu}m$. On the other hand, wafers incorporating intrinsic (i) a-Si:H as a passivation layer showed high quality passivation of a-Si:H/c-Si. The implied $V_{oc}$ of the ITO/p a-Si:H/i a-Si:H/n c-Si wafer/i a-Si:H/n a-Si:H/ITO stacked layers was 0.715 V for $50{\mu}m$ c-Si substrate, and 0.704 V for $170{\mu}m$ c-Si. The $V_{oc}$ in the heterojunction solar cells increased with decreases in the substrate thickness. The high quality passivation property on the c-Si led to an increasing of $V_{oc}$ in the thinner wafer. Short circuit current decreased as the substrate became thinner because of the low optical absorption for long wavelength light. In this paper, we show that high quality passivation of c-Si plays a role in heterojunction solar cells and is important in the development of thinner wafer technology.