• Title/Summary/Keyword: Minimum noise figure

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High-Gain Wideband CMOS Low Noise Amplifier with Two-Stage Cascode and Simplified Chebyshev Filter

  • Kim, Sung-Soo;Lee, Young-Sop;Yun, Tae-Yeoul
    • ETRI Journal
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    • v.29 no.5
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    • pp.670-672
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    • 2007
  • An ultra-wideband low-noise amplifier is proposed with operation up to 8.2 GHz. The amplifier is fabricated with a 0.18-${\mu}m$ CMOS process and adopts a two-stage cascode architecture and a simplified Chebyshev filter for high gain, wide band, input-impedance matching, and low noise. The gain of 19.2 dB and minimum noise figure of 3.3 dB are measured over 3.4 to 8.2 GHz while consuming 17.3 mW of power. The Proposed UWB LNA achieves a measured power-gain bandwidth product of 399.4 GHz.

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Analysis and extraction method of noise parameters for short channel MOSFET thermal noise modeling (단채널 MOSFET의 열잡음 모델링을 위한 잡음 파라메터의 분석과 추출방법)

  • Kim, Gue-Chol
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.13 no.12
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    • pp.2655-2661
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    • 2009
  • In this paper, an accurate noise parameters for thermal noise modeling of short channel MOSFET is derived and extracted. Fukui model for calculating the noise parameters of a MOSFET is modified by considering effects of parasitic elements in short channel, and it is compared with conventional noise model equation. In addition, for obtaining the intrinsic noise sources of devices, noise parameters(minimum noise figure $F_{min}$, equivalent noise resistance $R_n$ optimized source admittance $Y_{opt}=G_{opt}+B_{opt}$) in submicron MOSFETs is extracted. With this extraction method, the intrinsic noise parameters of MOSFET without effects of probe pad and extrinsic parasitic elements from RF noise measurements can be directly obtained.

Design of a 2.5V 2.4GHz Single-Ended CMOS Low Noise Amplifier (2.5V, 2.4GHz CMOS 저잡음 증폭기의 설계)

  • Hwang, Young-Sik;Jang, Dae-Seok;Jung, Woong
    • Proceedings of the IEEK Conference
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    • 2000.06e
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    • pp.191-194
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    • 2000
  • A 2.4 GHz single ended two stage low noise amplifier(LNA) is designed for Bluetooth application. The circuit was implemented in a standard digital 0.25 $\mu\textrm{m}$ CMOS process with one poly and five metal layers. At 2.4 GHz, the LNA dissipates 34.5 mW from a 2.5V power supply voltage and provides 24.6 dB power gain, 2.85 dB minimum noise figure, -66.3 dB reverse isolation, and an output 1-dB compression level of 8.5 dBm.

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A Study on the Analysis of Minimum Performance and Design for Receiver System in W-CDMA Handset (W-CDMA 단말기 수신 시스템에서 요구하는 최소성능 분석 및 설계에 관한 연구)

  • Kwack, Jun-Ho;Yun, Seok-Chul;Kim, Hak-Sun
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.9A
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    • pp.1005-1012
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    • 2004
  • In this paper, we have analyzed minimum performance required for W-CDMA Handset from standard and Implemented the receiver for W -COMA Handset. We have derived the noise figure and IIP3 of receiver and determined the selectivity about adjacent channel and minimum performance for front-end stage. Before the Implementation, we have verified the performance using AOS simulator In conclusion, we have implemented the receiver for W-COMA Handset using the heterodyne architecture and performed measurement. Therefore, this paper wlll gIVe a guideline for design of the W -COMA Handset.

A High Gain V-band CPW Low Noise Amplifier

  • Kang, Tae-Sin;Sul, Woo-Suk;Park, Hyun-Chang;Park, Hyung-Moo;Rhee, Jin-Koo
    • Proceedings of the IEEK Conference
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    • 2002.07b
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    • pp.1137-1140
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    • 2002
  • A V-band low-noise amplifiers (LNA) based on the Millimeter-wave monolithic integrated circuit (MIMIC) technology were fabricated using high performance 0.1 $\mu\textrm{m}$ $\Gamma$-shaped pseudomorphic high electron mobility transistors (PHEMT's), coplanar waveguide (CPW) structures and the integrated process for passive and active devices. The low-noise designs resulted in a two-stage MIMIC LNA with a high S$\sub$21/ gain of 14.9 dB and a good matching at 60 ㎓. 20 dBm of IP3 and 3.9 dB of minimum noise figure were also obtained from the LNA. The 2-stage LNA was designed in a chip size of 2.3 ${\times}$1.4 mm$^2$by using 70 $\mu\textrm{m}$ ${\times}$2 PHEMT’s. These results demonstrate that a good low-noise performance and simultaneously with a high gain performance is achievable with GaAs PHEMT's in the 60 ㎓ band.

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Noise Equivalent Differential Temperature of Passive FTIR Sensor System (수동형 퓨리에변환 적외선 분광기의 잡음등가온도지수)

  • Kang, Young-Il;Park, Byeong-Hwang;Choi, Myung-Jin;Hong, Dea-Sik;Choi, Soo;Kim, Dong-Hwan;Park, Do-Hyun
    • Journal of the Korea Institute of Military Science and Technology
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    • v.14 no.2
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    • pp.161-166
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    • 2011
  • The passive open-path Fourier-Transform-Infrared system was implemented for the toxic gas monitoring. Noise Equivalent Differential Temperature(NEDT) was investigated as a system performance evaluation figure and analyzed numerically with the designed parameters. Calculated NEDT was compared with the experimental value in the wavelength region of $700{\sim}1400cm^{-1}^$. The minimum detectable gas concentration was estimated from the obtained NEDT at the absorption wavelength of $SF_6$.

Fabrication and characterization of the 0.25 ${\mu}m$ T-shaped gate P-HEMT and its application for MMIC low noise amplifier (0.25 ${\mu}m$ T형 게이트 P-HEMT 제작 및 특성 평가와 MMIC 저잡음 증폭기에 응용)

  • Kim, Byung-Gyu;Kim, Young-Jin;Jeong, Yoon-Ha
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.36D no.1
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    • pp.38-46
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    • 1999
  • o.25${\mu}m$ T-shaped gate P-HEMT is fabricated and used for design of X0band three stage monolithic microwave integrated circuit(MMIC) low noise amplifier(LNA). The fabricated P-HEMT exhibits an extrinsis transconductance of 400mS/mm and a drain current of 400mA/mm. The RF and noise characteristics show that the current gain cut off frequency is 65GHz and minimum noise figure(NFmin) of 0.7dB with an associated gain of 14.8dB at 9GHz. In the design of the three stage LNA, we have used the inductive series feedback circuit topology with the short stub. The effects of series feedback to the noise figure, the gain, and the stability have been investigated to find the optimal short stub length. The designed three staage LNA showed a gain of above 33dB, a noise figure of under 1.2dB, and ainput/output return loss of under 15dB and 14dB, respectively. The results show that the fabricated P-HEMT is very suitable for a X-band LNA with high gain.

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0.11μm CMOS Low Power Broadband LNA design for 3G/4G LTE Environment (3G, 4G LTE 환경에 적합한 0.11μm CMOS 저전력, 광대역의 저잡음증폭기 설계)

  • Song, Jae-Yeol;Lee, Kyung-Hoon;Park, Seong-Mo
    • The Journal of the Korea institute of electronic communication sciences
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    • v.9 no.9
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    • pp.1027-1034
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    • 2014
  • We present the Low Power Broadband Low noise amplifier(LNA) that can be applied a whole bandwidth from 3G to 4G LTE. This multi input LNA was designed to steadily amplify through a multi input method regardless the size of the input signal and operate on a wide range of frequency band from a standard 3G CDMA band 1.2GHz to LTE band 2.5GHz. The designed LNA consumes an average of 6mA on a 1.2V power supply and this was affirmed using computer simulation tests. The amplification which was corresponded to the lowest input signal is at a maximum of 20dB and was able to obtain the minimum value of the gain of -10dB. The Noise figure is less than 3dB at a High-gain mode and is less than 15dB at a Low-gain mode.

A 30 GHz Band Low Noise for Satellite Communications Payload using MMIC Circuits (MMIC 회로를 이용한 위성중계기용 30GHz대 저잡음증폭기 모듈 개발)

  • 염인복;김정환
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.11 no.5
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    • pp.796-805
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    • 2000
  • A 30GHz band low noise amplifier module, which has linear gain of 30dB and noise figure of 2.6dB, for 30GHz satellite communication transponder was developed by use of MMIC and thin film MIC technologies. Two kinds of MMIC circuits were used for the low noise amplifier module, the first one is ultra low noise MMIC circuit and the other is wideband and high gain MMIC circuit. The pHEMT technology with 0.15$mu extrm{m}$ of gate length was applied for MMIC fabrication. Thin film microstrip lines on alumina substrate were used to interconnect two MMIC chips, and the thick film bias circuit board were developed to provide the stabilized DC bias. The input interface of the low noise amplifier module was designed with waveguide type to receive the signal from antenna directly, and the output port was adopted with K-type coaxial connector for interface with the frequency converter module behind the low noise amplifier module. Space qualified manufacturing processes were applied to manufacture and assemble the low noise amplifier module, and space qualification level of environment tests including thermal and vibration test were performed for it. The developed low noise amplifier was measured to show 30dB of minimum gain, $\pm$0.3dB of gain flatness, and 2.6dB of maximum noise figure over the desired operating frequency range from 30 to 31 GHz.

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Optimization of 70nm nMOSFET Performance using gate layout (게이트 레이아웃을 이용한 70nm nMOSFET 초고주파 성능 최적화)

  • Hong, Seung-Ho;Park, Min-Sang;Jung, Sung-Woo;Kang, Hee-Sung;Jeong, Yoon-Ha
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.581-582
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    • 2006
  • In this paper, we investigate three different types of multi-fingered layout nMOSFET devices with varying $W_f$(unit finger width) and $N_f$(number of finger). Using layout modification, we improve $f_T$(current gain cutoff frequency) value of 15GHz without scaling down, and moreover, we decrease $NF_{min}$(minimum noise figure) by 0.23dB at 5GHz. The RF noise can be reduced by increasing $f_T$, choosing proper finger width, and reducing the gate resistance. For the same total gate width using multi-fingered layout, the increase of finger width shows high $f_T$ due to the reduced parasitic capacitance. However, this does not result in low $NF_{min}$ since the gate resistance generating high thermal noise becomes larger under wider finger width. We can obtain good RF characteristics for MOSFETs by using a layout optimization technique.

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