• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.7 no.3
• /
• pp.130-134
• /
• 1982

In computer communication network, it is assumed that blocks are served at a rate of u messages per sec. The message blocks will be stayed in the buffer during the service time. In this case, the probability density distribution of the number of message blocks in the buffer space has been studied. When the average buffer space needed is minimum, the average block size will be specified by the relation between the input data and link infromation length. This relation proves to be perfect. The random number generator for this probability distribution is designed. The test result by making use of the random number generator has shown that is has little difference from the theoretical one.

• 지반과기술
• /
• v.3 no.3
• /
• pp.15-22
• /
• 2006

The optimum blasting pattern to excavate a quarry efficiently and economically can be determined based on the minimum production cost, which is generally estimated according to rock fragmentation. Therefore, it is a critical problem to predict fragment size distribution of blasted rocks over an entire quarry. By comparing various prediction models, it can be ascertained that the result obtained from Kuz-Ram model relatively coincides with that of field measurements. Kuz-Ram model uses the concept of rock factor to signify conditions of rock mass such as block size, rock jointing, strength and others. For the evaluation of total production cost, it is imperative to estimate 3-D spatial distribution of rock factor for the entire quarry. In this study, a sequential indicator simulation technique is adopted for estimation of spatial distribution of rock factor due to its higher reproducibility of spatial variability and distribution models than Kriging methods. Further, this can reduce the uncertainty of predictor using distribution information of sample data. The entire quarry is classified into three types of rock mass and optimum blasting pattern is proposed for each type based on 3-D spatial distribution of rock factor. In addition, plane maps of rock factor distribution for each ground level are provided to estimate production costs for each process and to make a plan for an optimum blasting pattern.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.4
• /
• pp.352-361
• /
• 2010

In this paper, a compact 20 W block-up-converter for C-band satellite communication is designed and implemented. The designed block up-converter consists of an intermediate frequency circuit, a mixer and local oscillator, a driver amplifier, a solid-state power amplifier, waveguide circuits, and a power supply module. To reduce the size of the block-up-converter, all circuits are assembled within an housing, so its dimension is just $21{\times}14{\times}11cm^3$. Especially, the waveguide filter and microstirp-to-waveguide transition are easily implemented using an housing. Also, to meet spurious and harmonics specification, various compact microstrip filters including an elliptic filter are integrated. Measurement results show that the developed block up-converter has good electrical performances: the output power of 43.7 dBm, the minimum gain of 65 dB, the gain flatness of ${\pm}1.84$, the IMD3 of -35 dBc, and the harmonic level of -105 dBc.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.44 no.2 s.314
• /
• pp.74-81
• /
• 2007

In this paper, an efficient SAD(Sum of Absolute Differences) processor structure for motion estimation of H.264 is proposed. SAD processors are commonly used both in full search methods for motion estimation and in fast search methods for motion estimation. Proposed structure consists of SAD calculator block, combinator block, and minimum value calculator block. Especially, proposed structure is simplified by using Distributed Arithmetic for addition operation. The Verilog-HDL(Hard Description Language) coding and FPGA(Field Programmable Gate Array) implementation results for the proposed structure show 39% and 32% gate count reduction in comparison with those of the conventional structure, respectively. Due to its efficient processing scheme, the proposed SAD processor structure can be widely used in size dominant H.264 chip.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.40 no.9
• /
• pp.373-383
• /
• 2003

In this paper we discuss the effect of the delay limit and the packet size related to the quality of service on a VoIP system using the Internet. We also provide a guideline to determining the optimal packet size of the voice data for a given delay limit. Empirical studies are done with two personal computers connected through the packet switched public IP network. The sender encodes the voice signal from the microphone to get PCM and ADPCM data and sends the data to the receiver using UDP packets. The receiver plays the reconstructed voice from the stream with lost and delayed packets. The quality of the reconstructed voice is evaluated offline by the MNB (Measuring Normal Block) method using the data acquired from the both sides. The result shows that under the delay limit of 100ms for 40Kbps, 32Kbps and l6Kbps of ADPCM data, the minimum packet size should be 300bytes, 400bytes and 600bytes respectively and the maximum packet size should be l200bytes commonly for the best quality of voice.

• ETRI Journal
• /
• v.36 no.2
• /
• pp.317-320
• /
• 2014

A balanced RF duplexer with low interference in an extremely narrow bandgap is proposed. The Long-Term Evolution band-7 duplexer should be designed to prevent the co-existence problem with the WiFi band, whose fractional bandgap corresponds to only 0.7%. By implementing a hybrid bulk acoustic wave (BAW) structure, the temperature coefficient of frequency (TCF) value of the duplexer is successfully reduced and the suppressed interference for the narrow bandgap is performed. To achieve an RF duplexer with balanced Rx output topology, we also propose a novel balanced BAW Rx topology and RF circuit block. The novel balanced Rx filter is designed with both lattice- and ladder-type configurations to ensure excellent attenuation. The RF circuit block, which is located between the antenna and the Rx filter, is developed to simultaneously function as a balance-tounbalance transformer and a phase shift network. The size of the fabricated duplexer is as small as $2.0mm{\times}1.6mm$. The maximum insertion loss of the duplexer is as low as 2.4 dB in the Tx band, and the minimum attenuation in the WiFi band is as high as 36.8 dB. The TCF value is considerably lowered to $-16.9ppm/^{\circ}C$.

• Journal of IKEEE
• /
• v.17 no.4
• /
• pp.459-468
• /
• 2013

Under nonlinear characteristics of frames, we propose the frame interpolation using GRNN to enhance the visual picture quality. By full search with block size of 128x128~1x1 to reduce blocky artifact and image overlay, we select the frame having block of minimum error and re-estimate the nonlinear moving vector using GRNN. We compare our scheme with forward(backward) motion compensation, bidirectional motion compensation when the object movement is large or the object image includes zoom-in and zoom-out or camera focus has changed. Experimental results show that the proposed method provides better performance in subjective image quality compared to conventional MCFI methods.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.26 no.7
• /
• pp.996-1003
• /
• 2022

In this paper, we present a new method for determining the scan line and range for vision-based 1-D barcode recognition. This is a study on how to detect valid barcode representative points and directions by applying the DBSCAN clustering method based on block HOG (histogram of gradient) and determine scan lines and barcode crosslines based on this. In this paper, the minimum and maximum search techniques were applied to determine the cross-line range of barcodes based on the obtained scan lines. This can be applied regardless of the barcode size. This technique enables barcode recognition even by detecting only a partial area of the barcode, and does not require rotation to read the code after detecting the barcode area. In addition, it is possible to detect barcodes of various sizes. Various experimental results are presented to evaluate the performance of the proposed technique in this paper.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.36S no.8
• /
• pp.81-87
• /
• 1999

In general, feature detection and tracking algorithms is classified by EBGM using Garbor-jet, NNC-R and STK algorithm using pixel eigenvalue. In those algorithms, EBGM and NCC-R detect features with feature model, but STK algorithm has a characteristics of an automatic feature selection. In this paper, to solve the initial problem of NR tracking in STK algorithm, we detected features using STK algorithm in modelled feature region and tracked features with NR method. In tracking, to improve the tracking accuracy for features by NR method, we proposed BMA-NR method. We evaluated that BMA-NR method was superior to NBMA-NR in that feature tracking accuracy, since BMA-NR method was able to solve the local minimum problem due to search window size of NR.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.3
• /
• pp.222-227
• /
• 2004

The sub-bitline (SBL) sensing voltage of a cell and total cell array can be measured by the method of SBL voltage evaluation method. The MOSAID tester can collect all SBL signals. The hierarchical bitline of unit cell array block is composed of the cell array of 2k rows and 128 columns, which is divided into 32 cell array sections. The unit cell array section is composed of the cell array of 64 rows and 128 columns. The average sensing voltage with 2Pr value of $5{\mu}C/cm^2$ and SBL capacitance of 40fF is about 700mV at 3.0V operation voltage. That is high compensation method for capacitor size degradation effect. Thus allowed minimum 2Pr value for high density Ferroelectric RAM (FeRAM) can move down to about less than $5{\mu}C/cm^2$.