• Journal of Advanced Navigation Technology
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• v.27 no.2
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• pp.197-202
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• 2023

This paper presents the design method and electrical characteristics of a high-efficiency power amplifier for a 50 Watts class repeater applied to a 5G system and used in in-building, subway, and tunnel. GaN was used for the termination transistor of the power amplifier designed here, and intermodulation signals were removed using DPD to satisfy linearity. In addition, in order to handle various requirements such as amplifier gain control and alarm processing required in the 5G system, the microprocessor is designed to exist inside the power amplifier. The amplifier manufactured to confirm the electrical performance of the power amplifier satisfying these conditions satisfied 46.5 dBm and the overall efficiency of the amplifier was 37%, and it was confirmed that it satisfied various alarm conditions and electrical characteristics required by telecommunication companies.

• Journal of the Korea Society of Computer and Information
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• v.14 no.12
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• pp.17-24
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• 2009

More recently, the Green Computing have become a important issue in all fields of industry. The energy efficiency cannot be over-emphasized. Microprocessor companies such as Intel Corporation design processors with taking both energy efficiency and performance into account. Nevertheless, general computer users typically utilize the CPU overclocking to enhance the application performance. The overclocking is traditionally considered as an evil in terms of the power consumption. In this paper, we present effective CPU overclocking schemes, which raise CPU frequency while keeping current CPU supply voltage for energy reduction and performance improvement. The proposed scheme gain both energy reduction and performance improvement. Evaluation results show that our proposed schemes reduce the processor execution time as much as 17% and total computer system energy as much as 5%, respectively. In addition, our effective CPU overclocking schemes reduce the Energy Delay Product (EDP) as much as 22%, on average.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.7
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• pp.454-461
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• 2007

Portable embedded systems have recently become smaller in size and offer a variety of junctions for users. These systems require high performance processors to handle the many functions and also a small battery to fit inside the system. However, due to its size, the battery life has become a major issue. It is important to have both efficient power design and management for each function, while optimizing processor voltage and clock frequency in order to extend the battery life of the system. In this paper, we calculated the efficiency of power in optimizing power rail. This system has two microprocessors. One is used to play music and movie files while the other is for DMB. In order to reduce power consumption, the DMB microprocessor is turned of while music or videos are played. Lastly, DVFS is applied to the processor in the system to reduce power consumption. Experimental results of the implemented system have resulted in reduced power consumption.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.51-58
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• 2007

This paper presented an adaptive pipeline architecture for a high-performance and low-power asynchronous processor. The proposed pipeline architecture employed a stage-skipping and a stage-combining scheme. The stage-skipping scheme can skip the operation of a bubble stage that is not used pipeline stage in an instruction execution. In the stage-combining scheme, two consecutive stages can be joined to form one stage if the latter stage is empty. The proposed pipeline architecture could reduce the processing time and power consumption. The proposed architecture supports multi-processing in the EX stage that executes parallel 4 instructions. We designed an asynchronous microprocessor to estimate the efficiency of the proposed pipeline architecture that was synthesized to a gate level design using a $0.35-{\mu}m$ CMOS standard cell library. We evaluated the performance of the target processor using SPEC2000 benchmark programs. The proposed architecture showed about 2.3 times higher speed than the asynchronous counterpart, AMULET3i. As a result, the proposed pipeline schemes and architecture can be used for asynchronous high-speed processor design

• KIPS Transactions on Software and Data Engineering
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• v.4 no.5
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• pp.219-224
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• 2015

In this paper, the designed fish robots DOMI ver1.0 is researched and development for aquarium underwater robot. The presented fish robot consists of the head, 1'st stage body, 2nd stage body and tail, which is connected two point driving joints. The model of the robot fish is analysis to maximize the momentum of the robot fish and the body of the robot is designed through the analysis of the biological fish swimming. Also, Lighthill was applied to the kinematics analysis of robot fish swimming algorithms, we are applied to the approximate method of the streamer model that utilizes techniques mimic the biological fish. The swimming robot has two operating mode such as manual and autonomous operation modes. In manual mode the fish robot is operated to using the RF transceiver, and in autonomous mode the robot is controlled by microprocessor board that is consist PSD sensor for the object recognition and avoidance. In order to the submerged and emerged, the robot has the bladder device in a head portion. The robot gravity center weight is transferred to a one-axis sliding and it is possible to the submerged and emerged of DOMI robot by the breath unit. It was verified by the performance test of this design robot DOMI ver1.0. It was confirmed that excellent performance, such as driving force, durability and water resistance through the underwater field test.

• Journal of Satellite, Information and Communications
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• v.2 no.2
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• pp.48-52
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• 2007

Recently, the research of GPS receiver which uses the Software-Defined Radio(SDR) technique is being actively proceeded instead of traditional hardware-based receiver. The software-based GPS receiver indicates that the signal acquisition and tracking treated by the hardware-based platform are processed as the software technique through a microprocessor. In this paper, GPS software receiver is designed by using SDR technique and then the signal acquisition, tracking, and the navigation message decoding parts are verified through the PC-based simulation. Moreover, the efficient algorithms are developed about the signal acquisition and tracking parts in order to obtain the accurate pseudorange. Finally, the pseudorange is calculated through the relative channel delay received through the different satellite of L1 frequency band. GPS software receiver proposed in this paper will be included in the element of GPS/Galileo complex system of development target and will provide not only the method that verifies the performance for Galileo Sensor Station standard but also usability by providing various debugging environments.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.6
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• pp.6-11
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• 2010

Amount of power generated from solar photovoltaic can vary according to solar flux of sunlight due to nature of solar cell panel, and an angle that the sun and the surface of cell makes brings difference in amount of power generation. Solar flux is decided by location of surface of the Earth that is classified into longitude and latitude, but on the other hand, an angle that the sung and the surface of cell makes can be changed by changing the angle of a solar power generation device at the fixed location. A method of changing the angle of a solar power generation device as a measure for improving practical power generation efficiency. and studies about a solar tracking device for this are in active. This study conducted a research on a solar tracking system for improvement of solar power generation efficiency. A solar tracking system of this study is composed of a sensor part to confirm a location of the sun with a semiconductor photosensor using the photo conductive effect, and it analyzed output signal of a sensor by using microprocessor and it produced a control signal of driving part for tracking the sun. A solar power generator (25W) was produced to analyze performance of a solar tracking system and usefulness of a solar tracking device that was designed and produced in this study was confirmed through experiments.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.28-37
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• 2010

In this paper, the IC (Integrated Circuit) for multi-channel asynchronous communication was designed by using FPGA and VHDL language. The existing chips for asynchronous communication that has been used commercially are composed of one to two channels. Therefore, when communication system with two channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 asynchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 256 bytes respectively and consequently high speed communication became possible. To detect errors between communications, it was designed with digital filter and check-sum logic and channel MUX logic so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. It was composed and simulated logic of VHDL described by using Cyclone II Series EP2C35F672C8 and QuartusII V8.1 of ALTERA company. In order to show the performance of designed IC, the test was conducted successfully in QuartusII simulation and experiment and the excellency was compared with TL16C550A of TI (Texas Instrument) company and ATmegal28 general-purpose micro controller of ATMEL company that are used widely as chips for asynchronous communication.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.5
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• pp.55-65
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• 2000

In this paper a new architecture of 24-bit two's complement adder is designed by using RB(Redundant Binary) arithmetic which has the advantage of CPF(Carry-Propagation-Free). A MPPL(Modified PPL) XOR/XNOR gate is applied to improve a TC2RB(Two's Complement to RB SUM converter) speed and to reduce the number of transistors, and we proposed two types adder which used a fast RB2TC(RB SUM to Two's Complement converter). The property of two types adder is followings. The improvement of TYPE 1 adder speed is archived through the use of VGS(Variable Group Select) method and TYPE 2 adder is through the use of a 64-bit GCG(Group Change bit Generator) circuit and a 8-bit TYPE 1 adder. For 64-bit, TYPE 1 adder can be expected speed improvement of 23.5%, 25.7% comparing with the CLA and CSA, and TYPE 2 adder can be expected 41.2%, 45.9% respectively. The propagation delay of designed 24-bit TYPE 1 adder is 1.4ns and TYPE 2 adder is 1.2ns. The implementation is highly regular with repeated modules and is very well suited for microprocessor systems and fast DSP units.

• Korean Journal of Optics and Photonics
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• v.4 no.1
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• pp.15-21
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• 1993

This paper describes the design and development of a KrF excimer laser stepper and discusses the detailed system parameters and characterization data obtained from the performance test. We have developed a deep UV step-and-repeat system, operating at 248 nm, by retrofitting a commercial modules such as KrF excimer laser, precision wafer stage and fused silica illumination and 5X projection optics of numerical aperture 0.42. What we have developed, to the basic structure, are wafer alignment optics, reticle alignment system, autofocusing/leveling mechanisms and environment chamber. Finally, all these subsystem were integrated under the control of microprocessor-based controllers and computer. The wafer alignment system comprises the OFF-AXIS and the TTL alignment. The OFF-AXIS alignment system was realized with two kinds of optics. One is the magnification system with the image processing technique and the other is He-Ne laser diffraction type system using the alignment grating on the wafer. 'The TTL alignment system employs a dual beam inteferometric method, which takes advantages of higher diffraction efficiency compared with other TTL type alignment systems. As the results, alignment accuracy for OFF-AXIS and TTL alignment system were obtained within 0.1 $\mu\textrm{m}$/ 3 $\sigma$ for the various substrate on the wafers. The wafer focusing and leveling system is modified version of the conventional systems using position sensitive detectors (PSD). This type of detection method showed focusing and leveling accuracies of about $\pm$ 0.1 $\mu\textrm{m}$ and $\pm$ 0.5 arcsec, respectively. From the CD measurement, we obtained 0.4 $\mu\textrm{m}$ resolution features over the full field with routine use, and 0.3 $\mu\textrm{m}$ resolution was attainable under more strict conditions.