• The Transactions of the Korean Institute of Electrical Engineers
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• v.38 no.1
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• pp.68-77
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• 1989

In this paper, a design approch is presented for a concurrent self-diagnosable microprocessor. An efficient diagnostic procedure to dynamically test the processor functional units decomposed by each insturction, concurrently with a program under execution is suggested. The basic goals of the proposed design approach are the low hardware overhead, no increase in the pin count and the minimal change of the initial design concepts on conventional microprocessors. The results of the performance of the suggested self-diagnosing hardware for an 8080 type microprocessor show that the suggested diagnosis scheme would be efficiently applicable, since diagnosing the processor functional units can be completed in a reasonably short time with the execution of an arbitrarily chosen sample program.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.83-90
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• 2004

In this paper, we proposed a new instruction set(X32Y ISA) with 3 different types of instruction mode. The proposed instruction set organizes 32-bit, 24-bit, 16-bit instruction in order to solves a problem of memory size limitation in an embedded microprocessor. We designed a 32-bit 5 stage pipeline RISC microprocessor based on the X32V ISA. To verify the proposed the X32V ISA and a microprocessor, we estimated a program code size of multimedia application programs using a X32V simulator. In result, we verified that the Light mode and the Ultra Light mode obtains 8%, 27% reduction of a program code size through comparison with the Default mode. The proposed microprocessor was verified all X32V instructions execution at Xilinx FPGA with 33MHz operating frequency,

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.885-888
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• 2005

In this study, we designed an ARM9 compatible RISC microprocessor using VHDL. The microprocessor was designed to support Harvard architecture with separate instruction cache and data cache. The state machine was optimized for multi-cycle instructions. In addition, a data forwarding mechanism was adopted to reduce the stall cycles due to data hazards. Assembly programs were up-loaded into a ROM block for system-level simulation. Proper operation of the designed microprocessor was confirmed by investigating the contents of the internal registers as well as the RAM block. Futhermore, the simulation results clearly indicated that the operation speed of the processor designed in this study is enhanced by reducing the execution cycles required for multiplication related instructions.

• Journal of Advanced Marine Engineering and Technology
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• v.11 no.2
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• pp.37-50
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• 1987

In an effort to conserve electric power, variable voltage variable frequency pulse width modulated (PWM) inverters are being applied increasingly to the variable speed control of the induction motors. The use of the PWM technique in motor drive applications is considered advantageous in many ways. For industrial applications, the PWM drive obtains its DC input through simple uncontrolled rectification of the commercial AC line and is favored for its good power factor, good efficiency, its relative freedom regulation problem, and mainly for its ability to operate the motor with nearly sinusoidal current waveforms. The purpose of this paper is to design a three phase natural sampled PWM inverter using microprocessor with simple control algorithm and hybrid control circuit has been built to implement this PWM scheme. In this system, the microprocessor can be used only for calculations directly related to motor control tasks by the design of hybrid circuit which sends PWM signals to the motor.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1978-1979
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• 2007

In this paper, the authors introduce a high-speed microprocessor based on automatic vacuum capacitor switch with a modified digital filter design using distributed arithmetic. The automation trends particularly the automatic vacuum capacitor switch has helped ameliorate the power factor essentials and automatically triggered to close when the line current exceeds rated value. Microprocessor relays use digital filters to extract only the fundamental and attenuate harmonics. To provide optimum speed characteristics a distributed arithmetic based filter design in the microprocessor controller which not only enhances filtering speed but additionally enables lower power consumption at the cost of area has been introduced. The result is a unified description that describes a digital filter structure down to bit level.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3233-3235
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• 1999

This paper describes development of a microprocessor-based optoelectronic guard system established a higher level of control reliability in machine guard design. The system uses the design concept of diverse redundancy and a fast software algorithm. We have accomplished an safety light curtain system that allows to be intentionally disabled moving machine by the interrupt of dangerous situations. As a result, it is showed that the proposed system is effective enough to practical applications.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2637-2640
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• 2003

In this paper, we propose a simple and efficient data input/output block with high speed between Motorola MPC8XX microprocessor and memory devices. Proposed method is capable of high speed data read and write using the address decoder and the burst cycle between Motorola PowerPC based MPC8XX microprocessor and fixed address locating memory devices such as FIFO, PCMCIA card, and so on. Experimental results are given our findings and discussions.

• Journal of the Korean Institute of Telematics and Electronics
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• v.16 no.3
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• pp.19-27
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• 1979

Microprocessor based digital filter was designed rising focus number system in order to increase the multiplication speed of microprocessor program. Addition and subtraction program was treated using look up table. The sampling speed was improved up to 500 samples per seconds on the third-order low- Pass digital filters.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.723-728
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• 1999

In this paper, we designed a Circular Path Built-In Self Test circuit and embedded it into a simple 8-bit microprocessor. Register cells of the microprocessor have been modified into Circular Path register cells and each register cells have been connected to form a scan chain. A BIST controller has been designed for controlling BIST operations and its operation has been verified through simulation. The BIST circuit described in this paper has increased size overhead of the microprocessor by 29.8% and delay time in the longest delay path from clock input to output by 2.9㎱.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.161-164
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• 2000

The architecture of microprocessor for a embedded system should be one that can perform more tasks with fewer instruction codes. The machine codes that high-level language compiler produces are mainly composed of specific ones, and codes that have small size are more frequently used. Extended Instruction Set Architecture (EISC) was proposed for that reason. We have designed pipe-line system for 64 bit EISC microprocessor. function level simulator was made for verification of design and instruction set architecture was also verified by that simulator. The behavioral function of synthesized logic was verified by comparison with the results of cycle-based simulator.