• ETRI Journal
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• 제33권5호
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• pp.731-740
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• 2011

Reconfigurable computing using a field-programmable gate-array (FPGA) device has become a promising solution in system design because of its power efficiency and design flexibility. To bring the benefit of FPGA to many application programmers, there has been intensive research about automatic translation from high-level programming languages (HLL) such as C and C++ into hardware. However, the large gap of syntaxes and semantics between hardware and software programming makes the translation challenging. In this paper, we introduce a new approach for the translation by using the widely used GCC compiler. By simply adding a hardware description language (HDL) backend to the existing state-of- the-art compiler, we could minimize an effort to implement the translator while supporting full features of HLL in the HLL-to-HDL translation and providing high performance. Our translator, called GCC2Verilog, was implemented as the GCC's cross compiler targeting at FPGAs instead of microprocessor architectures. Our experiment shows that we could achieve a speedup of up to 34 times and 17 times on average with 4-port memory over PICO microprocessor execution in selected EEMBC benchmarks.

• 한국정보통신학회논문지
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• 제17권5호
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• pp.1089-1094
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• 2013

본 논문에서는 모바일 디스플레이장치에 필요한 MDDI(Mobile Display Digital Interface) 프로토콜 패킷생성방법을 소프트웨어로 구현하는 것을 제안한다. 최소한의 하드웨어 구성을 가지며, 소프트웨어를 이용하여 MDDI 프로토콜 패킷을 생성한다. 이의 구현을 위해 고속 마이크로프로세와 FPGA(Field-Programmable Gate Array)로 하드웨어를 설계하였다. 소프트웨어로 생성한 패킷은 FPGA를 통해 LVDS(Low-Voltage Differential Signaling) 신호로 변환되어 출력된다. 제안하는 방식의 장점은 다양한 패킷을 소프트웨어로 쉽게 만들 수 있다는 것이다. 단점은 패킷전송에 걸리는 시간이 기존에 제안된 방식보다 빠르지 않았다. 이는 향후 개선되어야 할 과제로 남았다.

• 한국인터넷방송통신학회논문지
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• 제21권6호
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• pp.135-140
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• 2021

본 논문은 3축 가속도센서를 이용한 사고를 방지하기위한 시스템 설계에 관한 연구이다. 전원 공급단에 스위칭 파워 FET를 구성하였고, 전원 공급장치는 DC-DC, 레귤레이터, LDO를 설계하였다. 전원 문제를 한번에 해결하기 위해 2원화를 하였으며, 3축 가속도 센서를 설계하여 움직임 정보를 추출하여 안전하게 사고를 예방할 수 있도록 설계하였다. 마이크로프로세서는 I2C, UART 통신 포트를 통해 통신할 수 있도록 하였으며, J-LINK를 통해 디버깅 할 수 있도록 하였다. 가속도 센서 데이터 측정결과 30° 이상의 각도의 움직임을 감지했을 때 정상적으로 사고 방지를 위해 전원이 차단되는 것을 확인 할 수 있었다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1996년도 한국자동제어학술회의논문집(국내학술편); 포항공과대학교, 포항; 24-26 Oct. 1996
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• pp.1257-1260
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• 1996

This paper describes a fully digitalized driver for BLDC motors and the driver is realized by a single chip microprocessor. The speed change can be done by using the signal obtained from the position detecting sensor and adjusting the pulse width at the input channel of power module. In order to verify the effectiveness, an repetitive control method is adopted in the speed control tracking a periodic reference change in the BLDC motor system. The experimental results are shown for the reference tracking accurately according to the design parameter variation in the repetitive controller design.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1986년도 한국자동제어학술회의논문집; 한국과학기술대학, 충남; 17-18 Oct. 1986
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• pp.225-231
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• 1986

A design of an industrial microcomputer control system for an one-through tube boiler using oil is presented. The microcomputer system is based on standard iSBC 88/40 board. The software consist of a RTE(real time executive) and application tasks. The designed control system saves fuel and gives a more reliable over-all operation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(5)
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• pp.243-246
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• 2002

This paper presents a study on the design and implementation of modulized I/O buffer control system for large capacity cable check. A 8bit I/O buffer basic module which has feedback loops with input and output buffers is simulated in PSpice and implemented with logic gates. This system is composed of 18 sub-boards which have 3 channels of 32bit data buses, and of a main board with MPC860 microprocessor.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2003년도 춘계전력전자학술대회 논문집(2)
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• pp.769-772
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• 2003

In this paper are described design of hardware and GUI(Graphical User Interface) for a PC based Weighting System. Conventional Weighting System is adapted microprocessor system for measuring and controlling. This system should have big memory for the management of measured data and is difficult to operate. For such reason a new Weighting System based on PC is proposed. In this contribution is handled these problems.

• 한국정보통신학회논문지
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• 제5권7호
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• pp.1332-1339
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• 2001

SoC(System on Chip) 기술은 높은 융통성을 제공하므로 실장제어 분야에서 널리 활용되고 있다. 실장제어 시스템은 소프트웨어와 하드웨어를 동시에 개발하여야 하므로 많은 시간과 비용이 소요된다. 이러한 설계시간과 비용을 줄이기 위해 고급언어 컴파일러에 적합한 명령어 세트를 가지는 마이크로프로세서가 요구된다. 또한 FPGA(Field Programmable Gate Array)에 의한 설계검증이 가능해야 한다. 본 논문에서는 소형 실장제어 시스템에 적합한 EISC(Extendable Instruction Set Computer) 구조에 기반한 16 비트 FPGA 마이크로프로세서인 EISC16을 제안한다. 제안한 EISC16은 짧은 길이의 오프셋과 작은 즉치값을 가진 16 비트 고정 길이 명령어 세트를 가진다. 그리고 16 비트 오프셋과 즉치 값은 확장 레지스터와 확장 플래그를 사용하여 확장한다. 또한, IBM-PC와 SUN 워크스테이션 상에서 C/C++ 컴파일러 빛 응용 소프트웨어를 설계하였다. 기존 16 비트 마이크로프로세서들의 C/C++ 컴파일러를 만들고 표준 라이브러리의 목적 코드를 생성하여 크기를 비교한 결과 제안한 EISC16의 코드 밀도가 높음을 확인하였다. 제안한 EISC16은 Xilinx의 Vertex XCV300 FPGA에서 RTL 레벨 VHDL로 설계하여 약 6,000 게이트로 합성되었다. EISC16은 ROM, RAM, LED/LCD 판넬, 주기 타이머, 입력 키 패드, 그리고 RS-232C 제어기로 구성한 테스트 보드에서 동작을 검증하였다. EISCl6은 7MHz에서 정상적으로 동작하였다.

• 한국화재소방학회논문지
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• 제24권4호
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• pp.1-11
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• 2010

본 논문은 최근의 정보통신기술을 적용하여 아날로그 감지기와 화재경보시스템의 설계와 구현방법에 대한 사례를 기술하였다. 근거리와 원거리뿐만 아니라 중대형 규모의 건물에 설치할 수 있도록 감지기에서 부터 시스템까지 계층구조로 설계하였고, 대량의 이벤트를 효율적으로 처리하여 많은 정보를 보여주도록 통신프로토콜부터 응용프로그램까지 일관되게 설계하였다. PC 기반의 화재경보시스템은 Microprocessor 기반의 해외 제품보다 고속으로 대용량을 처리하고 큰 화면에 많은 정보를 제공한다. 그러므로 수천 개의 아날로그 감지기를 설치하는 대형건물도 하나의 시스템에 쉽게 수용할 수 있고 다중화장치를 이용하여 설치비용도 크게 절약할 수 있다. 본 시스템에서 구현된 경보시나리오는 경보가 발생할 때 비화재와 실화재를 구분하는데 큰 역할을 할 것으로 판단된다.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}