• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.414-420
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• 2005

The ShortStack Micro Server enables any product that contains a microcontroller or microprocessor to quickly and inexpensively become a networked, Internet-accessible device. The ShortStack Micro Server provides a simple way to add LonWorks networking to new or existing smart devices. . It implements the LonTalk protocol and provides the physical interface with the LonWorks communication. The ShortStack host processor can be an 8, 16, or 32-bit microprocessor or microcontrollers. The ShortStack API and driver typically require about 4kbytes of program memory on the host processor and less than 200 bytes of RAM. The interface between host processor and the ShortStack Micro Server may be a Serial Communication Interface (SCI). The LonWorks control module with a high performance is developed, which is composed of the 8 bit PIC Microprocessor for host processor and the smart neuron chip for the ShortStack Micro Server. This intelligent control board is verified as proceeding the various function tests from experimental system with an boost pump and inverter driving systems. It is also confirmed that the developed control module provides stably 0-10VDC linear signal to the input signal of inverter driving system for varying the induction motor speed. Thus, the experimental results show that the fabricating intelligent board carried out very well the various functions in the wide operating ranges of boost pump system. This developed control module expect to apply to industrial fields to require the comparatively exact control and monitoring such as multi-motor driving system with inverter, variable air volume system and the boost pump water supply systems.

• 대한전자공학회논문지
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• 제27권6호
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• pp.879-885
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• 1990

The geometrical algorithm for generating a 3-phase SPWM signal for VVVF (Variable Voltage, Variable Frequency) inverter drives is proposed. In this techniques, it is suitable for micro-processor based implementation since the pulsewiths are computable in real time from simple analytic expressions. System hardware consists of the inverter circuit and the 3-phase SPWM signal generating circuit. The inverter circuit is a 3-phase SPWM signal generating circuit is single board micro-processor consisting of Z-80A CPU, EPROMXI, CTC, PIO. The method of controlling VVVF at the inverter output is discussed here.

• Journal of Advanced Marine Engineering and Technology
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• 제35권2호
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• pp.288-294
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• 2011

본 논문에서는 FPGA기반의 SoC보드(Xilinx Virtex-4 ML401 EVM)를 이용한 전력인버터제어시스템을 설계하였다. 선박에 전력시스템을 적용하기 위해서 선박의 최신 통신 프로토콜인 NMEA 2000 표준 프로토콜을 적용하였으며 전력 시스템의 성능을 평가하기 위한 PC기반의 모니터링 프로그램을 제작하였다. 전력 제어시스템은 FPGA기반의 임베디드 SoC보드상에서 이중프로세서(Dualprocessor)형태로 설계하였으며 이중프로세서를 적용함으로써 실시간 제어 감시가 가능하다. 이중프로세서 중 하나는 전력 제어를 위한 PWM신호생성 및 전력 회로내의 주요 전력 파라미터를 센싱 하는 제어용 프로세서로 동작하며(Control processor) 다른 프로세서는 제어프로세서의 각종 전력 센서 파라미터와 제어 파라미터들을 이중포트 램(Dual Port RAM)을 이용하여 정보를 공유하고 외부 NMEA 2000프로토콜 기반의 모니터링 장치와 네트워크 기반의 통신을 수행하는 통신용 프로세서(Communication processor)로 구성된다. 본 논문에서 제작한 전력 제어시스템은 선박내의 분산발전,송배전 및 전압 레귤레이션 시스템에 적용 될 수 있다.

• 한국마린엔지니어링학회:학술대회논문집
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• 한국마린엔지니어링학회 2006년도 전기학술대회논문집
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• pp.249-250
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• 2006

In this paper, hardware design and implementation of digital controller for the High Precision Digital Power Supply (HPDPS) based on Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) is presented. Developed digital controller is composed of high resolution Digital Pulse Width Modulation (DPWM) and high resolution analog to digital converter circuit with anti-aliasing filter. And Digital Signal Processor (DSP) has the capability of a few micro-second calculation time for one feedback loop. 32-bit DSP and DPWM with 150[ps] step resolution is used to implement the HPDPS. Also 18-bit 2 mega sample per second ADC board is adopted for the developed digital controller. Also, hardware structure of the developed digital controller and experimental results of the first prototype board for HPDPS is described.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 추계학술대회 논문집
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• pp.615-616
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• 2006

A micro-fuel processor system integrating steam reformer and partial oxidation reactor was manufactured using low temperature cofired ceramic (LTCC). A CuO/ZnO/$Al_2O_3$ catalyst and Pt-based catalyst prepared by wet impregnation were used for steam reforming and partial oxidation, respectively. The performance of the LTCC micro-fuel processor was measured at various operating conditions such as the effect of the feed flow rate, the ratio of $H_2O/CH_3OH$, and the operating temperature on the LTCC reformer and CO clean-up system. The catalyst layer was loaded with "Fill and Dry" coating for small volume. The product gas was composed of $70\sim75%$ hydrogen, $20\sim25%$ carbon dioxide, and $1\sim2%$ carbon monoxide at $250\sim300^{\circ}C$, respectively.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1488-1491
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• 1987

This paper describes 16-point FFT processor using systolic array and its implementation into VLSI. Designed FFT processor executes FFT/IFFT arithmetic under mode control and consists of cell array, array controller and input/output buffer memory. For design for testibility, we added built-in self test circuit into designed FFT processor. To verify designed 16-point FFT processor, logic simulation was performed by YSLOG on MICRO-VAXII. From the simulation results, it is estimated that the proposed FFT processor can perform 16-point FFT in about 4400[ns].

• 대한전기학회논문지
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• 제34권6호
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• pp.230-237
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• 1985

Shortest path calculations for a large-scale network have to be performed using a decomposition techniqre, since the calculations require large memory size which increases by the square of the number of vertices in the network. Also, the calculation time increases by the cube of the number of vertices in the network. In the decomposition technique,the network is broken into a number of smaller size subnetworks for each of which shortest paths are computed. A union of the solutions provides the solution of the original network. In all of the decomposition algirithms developed up to now, boundary vertices which divide all the subnetworks have to be included in computing shortest paths for each subnetwork. In this paper, an improved algorithm is developed to reduce the number of boundary vertices to be engaged. In the algorithm, only those boundary vertices that are directly connected to the subnetwork are engaged. The algorithm is suitable for an application to real time computation using a parallel processor system which consists of a number of micro-computers or prcessors. The algorithm has been applied to a 39- vertex network and a 232-vertex network. The results show that it is efficient and has better performance than any other algorithms. A parallel processor system has been built employing an MZ-80 micro-computer and two Z-80 microprocessor kits. The former is used as a master processor and the latter as slave processors. The algorithm is embedded into the system and proven effective for real-time shortest path computations.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅲ
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• pp.1395-1398
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• 2003

This paper presents a 32-bit RISC Micro-Controller which is useful in the dedicated DSP and communication areas. The designed processor has 5 stages pipeline architecture, and 28 instructions. This RISC Micro-Controller consist of 22,100 gates and has 5.95 ns data arrival time, and 437 ㎽ total dynamic power. The RISC Micro-Controller is a IP (Intellectual property) Core module which can implement a number of protocols by and is applicable to DSP and data communication.

• 한국군사과학기술학회지
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• 제8권2호
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• pp.30-37
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• 2005

In this paper, we propose how to design a fire control system main control board for individual combat weapons using a small and low power processor. To design an electric board of small weapon systems, Size and power consumption are very important factors. We solved the problem using selection of an adaptive processor, introduction of MicroChipPackaging method, and separate design of a main board Also we applied these methods to make the fire control system for small arms.

• 전자진흥
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• 제7권11호
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• pp.99-99
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• 1987