• Journal of Korea Foundry Society
• /
• v.42 no.6
• /
• pp.331-336
• /
• 2022

In this study, we investigated the casting designs for fuel tank valves for LPG automobiles. The valves we studied have two cavities inside the part. There is inevitable air entrapment inside the cavities. In order to reduce this kind of casting defect, we carried out computer simulations of molten metal flow during the diecasting process of the target products. The main process parameters were the ingate position, product direction, and injection velocity. We also examined the possible use of vacuum diecasting. The position of the air entrapment was almost identical for all the ingate positions and product directions. We found that the change of the injection velocity affects the position of the air entrapment. In case of vacuum diecasting, the position of the air entrapment was similar to the previous cases, but it is expected that the air entrapment will be highly reduced in a real situation due to the vacuumed space.

• Proceedings of the IEEK Conference
• /
• 2004.06a
• /
• pp.221-224
• /
• 2004

This paper has researched on-chip spiral inductor in digital CMOS technology by modeling physical structure based on foundry parameter. To show the possibility of its application to RF design, we designed dual band RF front-end receiver. The simulated receiver have gain of 23/23.5 dB and noise figure of 2.8/3.36 dB at 2.45/5.25 GHz, respectively. It occupies $16mm^2$ in $0.25{\mu}m$ CMOS with 5 metal layer.

• Journal of Semiconductor Engineering
• /
• v.1 no.1
• /
• pp.57-63
• /
• 2020

Complementary metal-oxide-semiconductor (CMOS) technology is now facing a power scaling limit to increase integration density. Since 1970s, multi-valued logic (MVL) has been considered as promising alternative to resolve power scaling challenge for increasing information density up to peta-scale level by reducing the system complexity. Over the past several decades, however, a power-scalable and mass-producible MVL technology has been absent so that MVL circuit and system implementation have been delayed. Recently, compact MVL device researches incorporating multiple-switching characteristics in a single device such as 2D heterojunction-based negative-differential resistance (NDR)/transconductance (NDT) devices and quantum-dot/superlattices-based constant intermediate current have been actively performed. Meanwhile, wafer-scale, energy-efficient and variation-tolerant ternary-CMOS (T-CMOS) technology has been demonstrated through commercial foundry. In this review paper, an overview for MVL development history including recent studies will be presented. Then, the status and its future research direction of MVL technology will be discussed focusing on the T-CMOS technology for peta-scale information processing in semiconductor chip.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.20 no.4
• /
• pp.325-331
• /
• 2007

In this study, the inter-metal dielectric material of FSG was changed by low-k material in $0.13{\mu}m$ foundry-compatible technology (FCT) device process based on fluorinated silicate glass (FSG). Black diamond (BD) was used as a low-k material with a dielectric constant of 2.95 for optimization and yield-improvement of the low-k based device process. For yield-improvement in low-k based device process, some problems such as photoresist (PR) poisoning, damage of low-k in etch/ash/cleaning process, and chemical mechanical planarization (CMP) delamination must be solved. The PR poisoning was not observed in BD based device. The pressure in CMP process decreased to 2.8 psi to remove the CMP delamination for Cu-CMP and USG-CMP. $H_2O$ ashing process was selected instead of $O_2$ ashing process due to the lowest condition of low-k damage. NE14 cleaning after ashing process lot the removal of organic residues in vias and trenches was employed for wet process instead of dilute HF (DHF) process. The similar-state of SRAM yield was obtained in Cu/low-k process compared with the conventional $0.13{\mu}m$ FCT device by the optimization of these process conditions.

• Journal of Korea Foundry Society
• /
• v.11 no.6
• /
• pp.475-481
• /
• 1991

In this study the fabrication technology and mechanical properties of AC8A/$Al_2O_3$ Composites by squeeze casting process were investigated to develope for application as the piston materials that require good friction, wear resistance, and thermal stability. AC8A/$Al_2O_3$ composistes without a porosity and the break of preform were fabricated at the melt temperature of $740^{\circ}C$, the preform temperature of $500^{\circ}C$, and mold temperature of $400^{\circ}C$ under the applied pressure of $1200kg/cm^2$ as the results of the observation of microstructures. As the results of this study, the tensile strength of AC8A/$Al_2O_3$ composites was not increased linearly with $Al_2O_3$ volume fraction and so it seemed not to agree with the rule of mixture, which had been used often in metal matrix composite. Also the tensile strength after thermal fatigue test was little different from that before the test. Consequently it was thought that AC8A/$Al_2O_3$ composites fabricated under our experimental conditions had a good thermal stability and subsequently a good interface bonding. Wear rate(i.e., volume loss per unit sliding distance) of AC8A/$Al_2O_3$ composites was decreased with $Al_2O_3$ volume fraction and the sliding speed at both room temperature and $250^{\circ}C$ and so there was a good correlation between wear rate and hardness. Also the wear rate of AC/8A20% $Al_2O_3$ composities was obtained the value of $1.65cm^3/cm$ at sliding speed of 1.14m/sec as compared with about $3.0\;{\times}10^{-8}cm^3/cm$ hyereutectie Al-Si alloy(Al-16%Si-2%Cu-1%Fe-1%Ni), which applied presently for piston materials. The wear behavior of $Al_2O_3$ composites was observed to a type of abrasive wear by the SEM view of wear surface.

• Journal of Korea Foundry Society
• /
• v.43 no.6
• /
• pp.302-309
• /
• 2023

In general, castings often have complex shapes and significant variations in thickness within a single product, making grid generation for simulations challenging. Casting flows involve multiphase flows, requiring the tracking of the boundary between air and molten metal. Additionally, considerable time is spent calculating pressure fields due to density differences in a numerical analysis. For these reasons, the Cartesian grid system has traditionally been used in mold filling simulations. However, orthogonal grids fail to represent shapes accurately, leading to a momentum loss caused by the stair-like grid patterns on curved and sloped surfaces. This can alter the flow of molten metals and result in incorrect casting process designs. To address this issue, simulations in the Cartesian grid system involve creating a large number of grids to represent shapes more accurately. Alternatively, the Cut Cell method can be applied to address the problems arising from the Cartesian grid system. In this study, analysis results based on the number of grid in the Cartesian grid system for a casting flow analysis were compared with results obtained using the Cut Cell method. Casting flow simulations of actual products during various casting processes were also conducted, and these results were analyzed with and without applying the Cut Cell method.

• Journal of IKEEE
• /
• v.14 no.1
• /
• pp.33-39
• /
• 2010

In this paper, a 5Gb/s receiver with an adaptive equalizer for serial link interfaces is proposed. For effective gain control, a least-mean-square (LMS) algorithm was implemented with two internal signals of slicers instead of output node of an equalizing filter. The scheme does not affect on a bandwidth of the equalizing filter. It also can be implemented without passive filter and it saves chip area and power consumption since two internal signals of slicers have a similar DC magnitude. The proposed adaptive equalizer can compensate up to 25dB and operate in various environments, which are 15m shield-twisted pair (STP) cable for DisplayPort and FR-4 traces for backplane. This work is implemented in $0.18-{\mu}m$ 1-poly 4-metal CMOS technology and occupies $200{\times}300{\mu}m^2$. Measurement results show only 6mW small power consumption and 2Gbps operating range with fabricated chip. The equalizer is expected to satisfy up to 5Gbps operating range if stable varactor(RF) is supported by foundry process.