• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.109-109
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• 2006

Screen printing (SP) metal contact is typically applied to the solar cells for mass production. However, SP metal contact has low aspect ratio, low accuracy, hard control of the substrate penetration and unclean process. On the other hand, photo lithograpy (PL) metal contact can reduce defects by metal contact. In this investigation, PL metal contact was obtained the multi-layer structure of Ti/Pd/Ag by e-beam process. We applied SP metal contact and PL metal contact to single crystalline silicon solar cells, and demonstrated the difference of conversion efficiency. Because PL metal contact silicon solar cell has Jsc (short circuit current density) better than silicon solar cell applied SP metal contact.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.270-271
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• 2008

The contact resistance between organic semiconductor and source-drain electrode in Bottom Contact Organic Thin-Film Transistors (BCOTFTs) can be effectively reduced by metal oxide/molybdenum double layer structure; metal oxide layers including nickel oxide (NiOx/Mo) and moly oxide(MoOx) under molybdenum work as a high performance carrier injection layer. Step profiles of source-drain electrode can be easily achieved by simultaneous etching of the double layers using the difference etching rate between metal oxides and metal layers.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.318.2-318.2
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• 2014

The high contact resistance is still one of the major issues to be resolved in CdS/CdTe thin film solar cells. CdTe/Metal Schottky contact induced a high contact resistance in CdS/CdTe solar cells. It has been reported that the work function of CdTe thin film is more than 5.7 eV. There has not been a suitable back contact metal, because CdTe thin film has a high work function. In a few decades, some buffer layer was reported to improve a back contact problem. Buffer layers which are Te, $Sb_2Te_3$, $Cu_2Te$, ZnTe:Cu and so on was inserted between CdTe and metal electrode. A formed buffer layers made a tunnel junction. Hole carriers which was excited in CdTe film by light absorption was transported from CdTe to back metal electrode. In this report, we reported the variation of solar cell performance with different buffer layer at the back contact of CdTe thin film solar cell.

• Carbon letters
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• 제14권3호
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• pp.171-174
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• 2013

The high quality contact between graphene and the metal electrode is a crucial factor in achieving the high performance of graphene transistors. However, there is not sufficient research about contact resistance reduction methods to improve the junction of metal-graphene. In this paper, we propose a new method to decrease the contact resistance between graphene and metal using directly grown graphene over a metal surface. The study found that the grown graphene over copper, as an intermediate layer between the copper and the transferred graphene, reduces contact resistance, and that the adhesion strength between graphene and metal becomes stronger. The results confirmed the contact resistance of the metal-graphene of the proposed structure is nearly half that of the conventional contact structure.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2009년도 춘계학술발표대회
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• pp.22.2-22.2
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• 2009

Currently, metal silicides become increasingly more essential part as a contact material in complimentary metal-oxide-semiconductor (CMOS). Among various silicides, NiSi has several advantages such as low resistivity against narrow line width and low Si consumption. Generally, metal silicides are formed through physical vapor deposition (PVD) of metal film, followed by annealing. Nanoscale devices require formation of contact in the inside of deep contact holes, especially for memory device. However, PVD may suffer from poor conformality in deep contact holes. Therefore, Atomic layer deposition (ALD) can be a promising method since it can produce thin films with excellent conformality and atomic scale thickness controllability through the self-saturated surface reaction. In this study, Ni thin films were deposited by thermal ALD using bis(dimethylamino-2-methyl-2-butoxo)nickel [Ni(dmamb)2] as a precursor and NH3 gas as a reactant. The Ni ALD produced pure metallic Ni films with low resistivity of 25 $\mu{\Omega}cm$. In addition, it showed the excellent conformality in nanoscale contact holes as well as on Si nanowires. Meanwhile, the Ni ALD was applied to area-selective ALD using octadecyltrichlorosilane (OTS) self-assembled monolayer as a blocking layer. Due to the differences of the nucleation on OTS modified surfaces toward ALD reaction, ALD Ni films were selectively deposited on un-coated OTS region, producing 3 ${\mu}m$-width Ni line patterns without expensive patterning process.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.571-574
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• 2009

Metal oxide/metal bilayer structures are explored as contacts with a low injection barrier in organic thin-film transistors (OTFTs) in an effort to realize their true potential for low-cost electronics. OTFTs with a bilayer electrode of $WO_3$ (10nm) and Al shows a saturation mobility as large as 0.97 $cm^2$/Vsec which are comparable to those of Au-based control samples (~0.90 $cm^2$/Vsec). Scaling of contact resistance with respect to the thickness of $WO_3$ layer is also discussed.

• 한국산학기술학회:학술대회논문집
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• 한국산학기술학회 2002년도 춘계학술발표논문집
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• pp.106-108
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• 2002

반도체 physical layout design rule이 작아짐에 따라 Proximity effect와 overlay가 Pattern 구현에 크게 영향을 미치고 있다. Metal layer와 contact의 부족한 overlay margin으로 overlay 불량이 발생하고, 감소한 space margin으로 인해 bridge와 같은 문제가 나타난다. 따라서, resolution을 향상시키고, 최소한의 overlay margin을 확보함으로써 미세 pattern의 구현을 가능하게 한다. 이를 위해 OPC와 attPSM 같은 분해능향상기술이 사용된다. 그러나 attPSM의 사용은 원하지 않는 pattern이 생성되는 sidelobe와 같은 문제가 발생한다. 따라서 serial image simulation올 통해 추출한 rule을 rule-based correction에 적용하여 sidelobe현상을 방지한다. 그리고 overlay margin 부족으로 나타나는 문제는 metal layer와 contact overlap되는 영역의 line edge를 확장하고, rule checking을 통해 최소한의 space margin을 확보하여 해결한다 따라서 overlay error를 rule-based correction을 사용하여 효과적으로 방지한다.

• 대한금속재료학회지
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• 제49권11호
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• pp.905-909
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• 2011

The formation of front metal contact silicon solar cells is required for low cost, low contact resistance to silicon surfaces. One of the available front metal contacts is Ni/Cu plating, which can be mass produced via asimple and inexpensive process. A selective emitter, meanwhile, involves two different doping levels, with higher doping (${\leq}30{\Omega}/sq$) underneath the grid to achieve good ohmic contact and low doping between the grid in order to minimize the heavy doping effect in the emitter. This study describes the formation of a selective emitter and a nickel silicide seed layer for the front metallization of silicon cells. The contacts were thickened by a plated Ni/Cu two-step metallization process on front contacts. The experimental results showed that the Ni layer via SEM (Scanning Electron Microscopy) and EDX (Energy dispersive X-ray spectroscopy) analyses. Finally, a plated Ni/Cu contact solar cell displayed efficiency of 18.10% on a $2{\times}2cm^2$, Cz wafer.

• 전기학회논문지
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• 제59권1호
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• pp.130-133
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• 2010

Although many structures based on $SnO_2$ nanowires have been demonstrated, there is a limitation towards practical application due to the unwanted contact potential between the metal electrode and the $SnO_2$ nanowire. This is mostly due to the presence of the native oxide layer that acts as an insulator between the metal contact and the nanowire. In this study the contact properties between Ti/Au contacts and a single $SnO_2$ nanowire was compared to the electrical properties of a contact without the oxide layer. RIE(Reactive Ion Etching) is used to selectively remove the oxide layer from the contact area. The $SnO_2$ nanowires were synthesized by chemical vapor deposition (CVD) and dispersed on a $Si/Si_3N_4$ substrate. The Ti/Au (20nm/100nm) electrodes were formed bye-beam lithography, e-beam evaporation and a lift-off process.

• 한국산학기술학회:학술대회논문집
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• 한국산학기술학회 2003년도 춘계학술발표논문집
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• pp.239-242
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• 2003

Scale down으로 인해 부족해진 overlay margin을 통해 충분히 확보해주고, 이와 동시에 attPSM(attenuated phase shift)의 사용으로 발생하는 side-lobe 현상을 억제하기 위한 방법으로 rule-based OPC(optical proximity correction)룰 사용하여 side-lobe만을 효과적으로 추출한 후, 그 자리에 scattering bar를 삽입하였다. 그리고 ORC(optical rule checking)를 통해 original layout과 aerial image의 EPEs(edge placement errors)를 검사하여 검증에 걸리는 시간을 감소시켰다.