• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.6
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• pp.1242-1249
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• 2012

This paper proposes a metastability-free synchronization method and a mesochronous synchronizer for NoC. It uses the clock transmitted from TX as a strobe and solves the metastability problem by selecting one of rising or falling clock edge depending on the sampling value in RX when the phase difference between clocks is under a metastability window. The logic simulation results show that it works without metastability under $0^{\circ}{\sim}360^{\circ}$ phase difference in the synchronizer that a fault is inserted. The mesochronous synchronizer has a simple control logic and is suitable for NoC.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.10
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• pp.1123-1130
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• 2015

Network on a chip(NoC) is a communication subsystem between intellectual property(IP) cores in a SoC and improves high performance in the scalability and the power efficiency compared with conventional buses and crossbar switches. NoC needs a synchronizer to overcome the metastability problem between data links. This paper presents a new mesochronous synchronizer(MS) which is composed of selection window generator, selection signal generator, and data buffer. A delay line circuit is used to build selection window in selection window generator based on the delayed clock cycle of transmitted clock and the transmitted clock is compared with local clock to generate a selection signal in the SW(selection window). This MS gets rid of the restriction of metastability by choosing a rising edge or a falling edge of local clock according to the value of selection signal. The simulation results show that the proposed MS operates correctly for all phase differences between a transmitted clock and a local clock.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.12
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• pp.1345-1352
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• 2014

Bus architecture of SoC has been replaced by NoC in recent years. Noc uses the multi-clock domains to transmit and receive data between neighbor network interfaces and they have same frequency, but a phase difference because of clock skew. So a synchronizer is used for a mesochronous frequency in interconnection between network interfaces. In this paper the metastability is defined and analyzed in a D latch and a D flip-flop to search the possibilities that data can be lost in the process of sending and receiving data between interconnects when a local frequency and a transmitted frequency have a phase difference. 180nm CMOS model parameter and 1GHz are used to simulate them in HSpice. The simulation results show that the metastability happens in a latch and a flip-flop when input data change near the clock edges and there are intermediate states for a longer time as input data change closer at the clock edge. And the next stage can lose input data depending on environmental conditions such as temperature, processing variations, power supply, etc. The simulation results are very useful to design a mescochronous synchronizer for NoC.